Hi,
In the AM5716 datasheet (SPRS957I) on page 158 there is a maximum allowed clock for QSPI_FCLK of 128MHz.
QSPI_FCLK is sourced from QSPI_GFCLK that can either be FUNC_256M_CLK/2 or PER_QSPI_CLK. With a divider of 1, 2 or 4.
ROM code default clock setting for PER_QSPI_CLK is 192MHz as of Technical Reference Manual (SPRUHZ7I) page 7515.
ROM code default clock setting for FUNC_256M_CLK is 256MHz as of Technical Reference Manual (SPRUHZ7I) page 7515.
ROM code default clock setting for QSPI_SCLK is 48MHz as of Technical Reference Manual (SPRUHZ7I) page 7540.
48MHz can only be generated from 192MHz and not from 128MHz (256MHz/2).
Is this 128MHz limit for QSPI_FCLK a typo in the datasheet?
If not how does the ROM code generate this 48MHz for QSPI_SCLK?
Best regards,
Patrick
