Part Number: TMDS64GPEVM
We adapted the r5 baremetal MSI IRQ End Point example from AM64x MCU+ SDK 08.06.00.43 to work with a main board
using an embedded linux platform.
We can detect successfully the TI board as a PCI device, request one MSI interrupt and register an IRQ handler.
We have been successful at reconfiguring the outbound Address Translation Unit(ATU) to the MSI address given by
the root complex. Therefore, the EP sees that RC has enabled MSI interrupts and sends one MSI to our linux RC.
The problem we encountered is that our linux was not receiving the interruption. Debugging through the TI PCIe
API from the SDK, we found that the MSI data sent with the MSI message is being modified (see function int32_t
Pcie_epSendMsiIrq() at pcie_soc.c:962). We suspect this is the issue that makes our linux not receive the IRQ.
To test this suspicion, we have modified "MSI data" back to the original value given by the linux RC using the
debugger while stepping through the API. If we do so, the linux does indeed receive and handle the IRQ, but
additional unexpected interrupts are also being received.
Our questions are:
1.- Why does the API modify the "MSI data" value assigned by the root complex?
2.- Is our TI EP generating multiple MSI interrupts when we change "MSI data" in order to be received by the RC,
due to some interaction with the PCIe hardware that we are not aware of?
Thanks for your attention.
