TMS320C6655: Clock generator for TMS320C6655

Hi Daniel,

I'm from the clock generator applications team. I know the CDCE6214 quite well but am not familiar with the TMS320C6655 device. Looking through the datasheet, I see the following reference clocks: Core Clock, SerDes, DDR, PCIe, and HyperLink:

• CORECLK:
  • 100 ps of max jitter
• SerDes:
  • 4-8 ps of max jitter
• DDR:
  • 0.025 * tc(DDRCLKN) ps of max jitter
• PCIe:
  • 4 ps of max jitter
• HyperLink:
  • 4 ps of max jitter

CDCE6214's typical jitter values range between 0.35 - 2.7 ps so the outputs would most likely be fine for these clocks (not sure how to interpret the DDR jitter specification). However I don't know the intended clock formats or the exact frequencies, I know the PCIe reference clock is typically 100 MHz HCSL but I have not worked with the other types. In addition, the CDCE6214 has four differential outputs + one LVCMOS output, so if all five of these DSP clocks are differential, then one CDCE6214 device would not be sufficient.

kcastille, are you or someone on your team familiar with the clocking requirements from the TMS320C6655's perspective?

Thanks,

Evan Su

Hi Daniel,

The design guide that Kyle linked says that it has an internal 100 Ohm termination:

Best,

Evan Su