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SK-AM64: Baremetal configuration of CSPW

Abhimanyu Singh
Prodigy 187 points

Part Number: SK-AM64

Hi

void InitializeEthernet()
{
    _mainpadconfig->PADCONFIG126 = BIT18|BIT16|0x4;//18MDIO
    _mainpadconfig->PADCONFIG127 = BIT16|0x4;//19MDC
    _mainpadconfig->PADCONFIG158 = BIT21|BIT18|BIT16|0x0;//EXTI

    _mainpadconfig->PADCONFIG71 = BIT21|BIT18|BIT16|0x4;
    _mainpadconfig->PADCONFIG74 = BIT21|BIT18|BIT16|0x4;
    _mainpadconfig->PADCONFIG84 = BIT21|BIT18|BIT16|0x4;
    _mainpadconfig->PADCONFIG85 = BIT21|BIT18|BIT16|0x4;
    _mainpadconfig->PADCONFIG51 = BIT21|BIT18|BIT16|0x4;
    _mainpadconfig->PADCONFIG54 = BIT21|BIT18|BIT16|0x4;
    _mainpadconfig->PADCONFIG73 = BIT16|0x4;
    _mainpadconfig->PADCONFIG75 = BIT16|0x4;
    _mainpadconfig->PADCONFIG76 = BIT16|0x4;
    _mainpadconfig->PADCONFIG83 = BIT16|0x4;
    _mainpadconfig->PADCONFIG55 = BIT16|0x4;
    _mainpadconfig->PADCONFIG56 = BIT16|0x4;

    _mainpadconfig->PADCONFIG66 = BIT21|BIT18|BIT16|0x2;
    _mainpadconfig->PADCONFIG67 = BIT21|BIT18|BIT16|0x2;
    _mainpadconfig->PADCONFIG68 = BIT21|BIT18|BIT16|0x2;
    _mainpadconfig->PADCONFIG69 = BIT21|BIT18|BIT16|0x2;
    _mainpadconfig->PADCONFIG70 = BIT21|BIT18|BIT16|0x2;
    _mainpadconfig->PADCONFIG72 = BIT21|BIT18|BIT16|0x2;
    _mainpadconfig->PADCONFIG77 = BIT16|0x2;
    _mainpadconfig->PADCONFIG78 = BIT16|0x2;
    _mainpadconfig->PADCONFIG79 = BIT16|0x2;
    _mainpadconfig->PADCONFIG80 = BIT16|0x2;
    _mainpadconfig->PADCONFIG81 = BIT16|0x2;
    _mainpadconfig->PADCONFIG82 = BIT16|0x2;

    _mainpadconfig->PADCONFIG98 = BIT16|0x7;
    _mcupadconfig->PADCONFIG5   = BIT16|0x7;

    SOC_moduleClockEnable(TISCI_DEV_CPSW0,1);
    SOC_moduleClockEnable(TISCI_DEV_DMASS0,1);

    for(uint32 i=0;i< (2 *100);i++);
    _cpsw->mdio.CONTROL &= (~0xFF | 99);
    _cpsw->mdio.CONTROL &= ~BIT31;
    _cpsw->mdio.CONTROL |= BIT24;
    _cpsw->mdio.CONTROL |= BIT30;

    uint16 phyregisters0[0x1DF];
    uint16 phyregisters1[0x1DF];
    uint32 status=0;

    for(uint32 i=0;i<0x1DF;i++)status = MDIO_phyExtRegRead((uint32)&_cpsw->mdio, NULL, 0, i, &phyregisters0[i]);
    phyregisters0[0x0000] |= BIT09;     status = MDIO_phyExtRegWrite((uint32)&_cpsw->mdio, NULL, 0, 0x0000, phyregisters0[0x0000]);
    phyregisters0[0x0018] = 0x2232;     status = MDIO_phyExtRegWrite((uint32)&_cpsw->mdio, NULL, 0, 0x0018, phyregisters0[0x0018]);
    phyregisters0[0x0032] |= BIT07;     status = MDIO_phyExtRegWrite((uint32)&_cpsw->mdio, NULL, 0, 0x0032, phyregisters0[0x0032]);
    phyregisters0[0x00E9] = 0xDF22;     status = MDIO_phyExtRegWrite((uint32)&_cpsw->mdio, NULL, 0, 0x00E9, phyregisters0[0x00E9]);
    phyregisters0[0x001F] = BIT14;      status = MDIO_phyExtRegWrite((uint32)&_cpsw->mdio, NULL, 0, 0x001F, phyregisters0[0x001F]);
    for(uint32 i=0;i< (200 *100);i++);

    for(uint32 i=0;i<0x1DF;i++)status = MDIO_phyExtRegRead((uint32)&_cpsw->mdio, NULL, 1, i, &phyregisters1[i]);
    phyregisters1[0x0000] |= BIT09;     status = MDIO_phyExtRegWrite((uint32)&_cpsw->mdio, NULL, 1, 0x0000, phyregisters1[0x0000]);
    phyregisters1[0x0018] = 0x2232;     status = MDIO_phyExtRegWrite((uint32)&_cpsw->mdio, NULL, 1, 0x0018, phyregisters1[0x0018]);
    phyregisters1[0x0032] |= BIT07;     status = MDIO_phyExtRegWrite((uint32)&_cpsw->mdio, NULL, 1, 0x0032, phyregisters1[0x0032]);
    phyregisters1[0x001F] = BIT14;      status = MDIO_phyExtRegWrite((uint32)&_cpsw->mdio, NULL, 1, 0x001F, phyregisters1[0x001F]);
    for(uint32 i=0;i< (200 *100);i++);

    volatile uint32 *CTRLMMR_ENET1_CTRL = ((volatile uint32*)(0x43004044));
    volatile uint32 *CTRLMMR_ENET2_CTRL = ((volatile uint32*)(0x43004048));
    *CTRLMMR_ENET1_CTRL = 2;
    *CTRLMMR_ENET2_CTRL = 2;

    _cpsw->control.CONTROL = BIT15|BIT14|BIT02;

    _cpsw->control.PTYPEREG = 0x2;

    _cpsw->control.VLANLTPYE = 0x88A88100;

    _cpsw->control.FREQUENCY = 250;

    _cpsw->control.P0RXMAXLEN = 1518;

    _cpsw->control.STATPORTEN =  BIT02|BIT01|BIT00;

    _cpsw->ale.CONTROL |=  BIT31;
    _cpsw->ale.CONTROL |=  BIT30;
    _cpsw->ale.CONTROL |=  BIT04;

    _cpsw->control.P0CONTROL|= BIT01|BIT00;
    _cpsw->control.P1CONTROL|= BIT01;
    _cpsw->control.P1SAL = 0xABCD;
    _cpsw->control.P1SAH = 0xCDEF0000;
    _cpsw->control.P1MACCONTROL = BIT24|BIT23|BIT22|BIT07;

}

I wrote the above code to configure CPSW. The PAD config and MDIO are working good. I have tested them using PRUICSSG and the PRU is recieving and transmitting data OK.

Now I am trying to do this using CPSW instead of PRUs

I am not sure about the CPSW part if it is configure correctly or not. Are these many regesters enough to configure CPSW to recieve data or am I missing any, or is the order incorrect? Because the statistics register on all ports are dead and 0, showing no activity even thgought the ethernet jack recieve LED is blinking.

Thanks

  • 0
    TI__Mastermind 19610 points

    Hi ,

    Thanks for your query.

    I need to work with dev team to check on this.

    Please allow me some to time to get back to you.

    Best Regards

    Ashwani

  • 0
    Prodigy 187 points

    Hi,

    I played around a lot and found the problem. It is was actually problem with CPSW_PN_MAC_CONTROL_REG_k which in my code is on line number 89 i.e. _cpsw->control.P1MACCONTROL. Apparently I forced the MAC into gigabit mode and the statistics numbers came alive and started incrementing. Following is the new register config

    _cpsw->control.P1MACCONTROL = BIT24|BIT23|BIT22|BIT17|BIT07|BIT05|BIT00;

    Hope it helps someone in the future