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[FAQ]AM64X : How to Route MCU GPIO Interrupts to MAIN Domain Cores in MCU PLUS SDK Version 6.0 & above ?

Swargam Anil
Mastermind 28990 points
Part Number: AM6442
Other Parts Discussed in Thread: SYSCONFIG

I am trying to modify the gpio_input_interrupt example for the R5F0-0 core to work with MCU_GPIO0 pins and run it on the R5 core from the CCS debug session, but for now unsuccessfully.

 Unfortunately, the SysConfig tool doesn't seem to allow routing MCU_GPIOMUX_INTROUTERS to the R5 core, as the only visible options for interrupt router output are MAIN_GPIOMUX_INTROUTERS. As a workaround, I copied files generated from the syscfg file and tried to modify the rmIrqReq.dst_host_irq parameter in the Sciclient_gpioIrqSet function manually, similarly to the FAQ tutorial for AM6442 (the difference is there is no board.c file, so I modified the generated ti_drivers_config.c), but this also doesn't work and results in a SCIClient error.

How can I solve this problem ?

  • +1
    TI__Mastermind 28990 points

    The problem is that the DMSC core is not allowing interrupt routing to the main domain for MCU peripherals.

    In new versions of MCU+SDK 8.6, DMSC software control is divided into two parts: MCU domain control and main domain control.

    The DMSC core should allow the user to route MCU GPIO interrupt router outputs to the main domain by default. But this was not happening in the new version of MCU+SDK.

    Now, coming to the 8.6 MCU+ SDK, all the board configurations are compiled into the board configuration binary with the main domain device group ID. This causes a mismatch in the device group ID for the MCU domain peripherals, which leads to the failure of the RM configuration of the MCU GPIO Interrupt Router.

    To fix this issue, we need to follow the steps below.

    I have used the below-highlighted function in the SBL to inform the DMSC core. Hey, route MCU GPIO interrupts or other MCU GPIO interrupt routers to the main domain. After adding this function, I am able to route MCU GPIO interrupts to main domain peripherals.

     

    Step 1:  Route MCU GPIO interrupts to the R5F core. For that, I have updated the sciclient_defaultBoardcfg_rm file.

    In current version 8.6 MCU+SDK  below router output is routed to the A53 core ; it should route to the R5F core for your Application . So, I have updated it.

    You can choose your destination core based on your requirement .

    Please use the above FAQs for how to update this file and compile it.

    Step 2: Compile the sciclient_defaultBoardcfg_rm file by using the above FAQ.

    Step 3: Allow the DMSC core that the Route MCU GPIO interrupt Router outputs to the MAIN domain for MCU peripherals as per the below image in the SBL project .

    Step 4: Compile the SBL

    Step 5: Flash the SBL OSPI updated bin file on the Target.

    Step 6: System configuration is generating the wrong code while selecting the MCU GPIO pin. So, please disable interrupts from the system configuration as per the below image.

     

    Step 7: Enable Interrupt manually as per the below image.

     

    Step 8: Please see the below image for SCI client configuration to route MCU GPIO interrupts to the R5F core.