AM6442: What is the impact of injecting L2 cache exceptions？

lina zhang

Part Number: AM6442

Hi, experts:

On the architecture,Core 0 and core 1 share an L2 cache on Arm Cortex-A53.Will injecting L2 cache exceptions on core 0 ,affect core 1? For example, which core or both will be affected such as double error? Is there any more detailed information on ECC testing that can be provided to us.

over 1 year ago

0 Mukul Bhatnagar over 1 year ago

TI__Guru* 81115 points

Hello Lina

TI does does not use ARM's STL internally, you will need to acquire STLs directly from ARM. Regarding support for STL, as there is no internal reference on the TI side and we cannot provide guidance on these questions

The only pointers we have is what was provided in the previous post from Neelima

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1219056/am6442-how-to-obtain-the-iec61508-functional-security-document-corresponding-to-am64x/4612676?tisearch=e2e-sitesearch&keymatch=STL#4612676

Regards

Mukul

0 Neelima Muralidharan over 1 year ago in reply to Mukul Bhatnagar

TI__Expert 6530 points

Hi Mukul,

I think the question is more related to error injection for L2 cache to test the ecc correction and detection logic associated with L2 cache.

Lina,

Yes this could potentially impact core1. Please read more about error reporting here https://developer.arm.com/documentation/ddi0500/j/Cache-Protection/Error-reporting

Let us know if you have more questions.

Regards,
Neelima

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AM6442: What is the impact of injecting L2 cache exceptions？