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AM6442: What is the impact of injecting L2 cache exceptions?

Part Number: AM6442

Hi, experts:

On the architecture,Core 0 and core 1 share an L2 cache on Arm Cortex-A53.Will injecting L2 cache exceptions on core 0 ,affect core 1? For example, which core or both will be affected such as double error? Is there any more detailed information on ECC testing that can be provided to us.