Hello,
I have been trying to set up a boundary scan test on one of our new board configurations that is using the AM6254 processor. I am having problems with the following processor pins:
mcu_spi0_clk(#A7)
mcu_spi0_d0(#D9)
vout0_data1(#V24)
vout0_data3(#W24)
vout0_data4(#Y25)
vout0_data6(#Y23)
vout0_data7(#AA25)
vout0_data8(#V21)
I'm still investigating, but from what I've established all of the vout0 pins and the mcu_spi0_clk pin seem to be unable to drive or read correctly. The mcu_spi0_d0 pin is acting like it is connected to the mcu_spi0_d1 pin.
There is nothing else connected to these pins except the external PLD device(s) that can drive or read to verify the connection. Compliance pattern is good and the processor is reset before boundary scan is run as described in the design warning. Over a hundred other signals are working without issue. I checked the errata and nothing is listed regarding these signals.
Are you aware of any issues with JTAG boundary scan on these signals? Are you able to test this behavior yourself?
Thanks,
Josh