We are developing our product using the am6442 chip and our product requires SIL3 security certification. I am researching the diagnosis based on A53 core cache ecc (including L1 Dcache and L2 Cache). At first, my idea was to inject error by setting the registers of A53(CPUACTLR.L1DEIEN and L2ACTLR.L2DEIEN ).
However, after reading the arm manual（https://developer.arm.com/documentation/ddi0500/j/Cache-Protection/Error-injection）and related discussion post(e2e.ti.com/.../am6442-what-is-the-impact-of-injecting-l2-cache-exceptions, the method can affect the normal operation of the system. I would like to consult with TI experts. Do you have any good ideas about the diagnosis of A53 cache ecc? Looking forward to your reply, thank you。