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Original question:

AM6442: How to enable the L1 Cache and L2 Cache ECC Protection on Arm Cortex-A53?

AM6442: About the diagnosis of A53 cache ecc

jian zhao
Prodigy 20 points
Part Number: AM6442

Hello experts

We are developing our product using the am6442 chip and our product requires SIL3 security certification. I am researching the diagnosis based on A53 core cache ecc (including L1 Dcache and L2 Cache). At first, my idea was to inject error by setting the registers of A53(CPUACTLR.L1DEIEN and L2ACTLR.L2DEIEN ).

However, after reading the arm manual（https://developer.arm.com/documentation/ddi0500/j/Cache-Protection/Error-injection）and related discussion post(e2e.ti.com/.../am6442-what-is-the-impact-of-injecting-l2-cache-exceptions, the method can affect the normal operation of the system. I would like to consult with TI experts. Do you have any good ideas about the diagnosis of A53 cache ecc? Looking forward to your reply, thank you。

  • 0
    Prodigy 20 points

    I found in TI's user manual that the TI chip supports error injection, but I am not sure how to use it. Could you provide a method and explain the impact of this method?

  • 0 in reply to jian zhao
    TI__Mastermind 24840 points

    The error injection is part of the software diagnostics library (SDL) that is part of the MCU+ SDK. See https://software-dl.ti.com/mcu-plus-sdk/esd/AM64X/latest/exports/docs/api_guide_am64x/SDL_ECC_PAGE.html for  description and examples. In general the design is for error injection tests to be run prior to safety function running, so for example during initialization prior to normal operation with an active safety function.

    As a note on SIL levels a single AM64x device main domain including the A53's is designed to meet SIL-2 level of random faults. See Section 2 in the safety manual:

    "Includes sufficient functional safety mechanisms for random fault integrity requirements of SIL-2 for the entire device (MCU domain and Main domain)."

    To meet SIL-3 there will have to be further components such as a second SIL-2 channel.

      Pekka

  • 0 in reply to Pekka Varis
    Prodigy 20 points

    Thank you for your timely reply. I have two more questions to help you answer,thank you.

    1) I still haven't found any relevant descriptions for A53 L2 cache ECC diagnosis and L1 Dcache ECC diagnosis in the SDK documentation. Could you help me point out what values eccMemType and memSubType represent for A53 L2 cache and A53 L1 Dcache?

    2) Is it feasible for us to perform the ECC diagnostic on A53 L2 cache and L1 Dcache every hour during normal system operation? Will the ECC diagnostic method affect the normal operation of the system?