This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

[FAQ] AM62: What is the Time Sync Router for? How do I use it?

Part Number: AM625

AM62 has interrupt routers, just like any other processor. But it also has an interrupt router called the Time Sync Router (TSR) that is designed to route an input interrupt to multiple output interrupts. What is the TSR for? The documentation is not very clear at the moment, so how do I use it?

  • For basic information about what the Time Sync Router (TSR) is and how it works, reference the AM64x version of this FAQ: 

    Worst-case latencies 

    For additional information, reference the AM64x version of this FAQ.

    The input latency for AM62 will be less than 12ns.

    When we tested router + output latency, we split it into two cases:
    Case 1: Test all TSR outputs that are inside the AM62 processor (e.g., PRU and a CPTS are inside the AM62 processor)
    Case 2: Test all possible TSR outputs, including the SYNC_OUT processor pins

    For Case 1, the router + output latency is more than 0ns, and less than 7ns. Thus, the difference in time for a single input to reach two different outputs inside the processor will always be less than 7ns.
    For Case 2, the router + output latency is more than 0ns, and less than 15ns. Thus, the difference in time for a single input to reach two different outputs when one of the outputs is a processor pin will always be less than 15ns.

    TSR inputs 

    See TRM section "Time Synchronization Support", table "TimeSynch_Event_Introuter" (table name may change in future TRM revisions).

    TSR outputs 

    As of AM62 TRM revision A, these are not listed anywhere.

    A visual summary of inputs and outputs is here:

    And the number associated with each output is listed below:

    timesync_event_introuter_out_0 dmss_am62_main_0_intaggr_0.intaggr_levi_pend.8
    timesync_event_introuter_out_1 dmss_am62_main_0_intaggr_0.intaggr_levi_pend.9
    timesync_event_introuter_out_2 dmss_am62_main_0_intaggr_0.intaggr_levi_pend.10
    timesync_event_introuter_out_3 dmss_am62_main_0_intaggr_0.intaggr_levi_pend.11
    timesync_event_introuter_out_4 dmss_am62_main_0_intaggr_0.intaggr_levi_pend.12
    timesync_event_introuter_out_5 dmss_am62_main_0_intaggr_0.intaggr_levi_pend.13
    timesync_event_introuter_out_6 dmss_am62_main_0_intaggr_0.intaggr_levi_pend.14
    timesync_event_introuter_out_7 dmss_am62_main_0_intaggr_0.intaggr_levi_pend.15
    timesync_event_introuter_out_8 icss.pr1_edc0_latch0_in
    timesync_event_introuter_out_9 icss.pr1_edc0_latch1_in
    timesync_event_introuter_out_10 cpsw.cpts_hw1_push
    timesync_event_introuter_out_11 cpsw.cpts_hw2_push
    timesync_event_introuter_out_12 cpsw.cpts_hw3_push
    timesync_event_introuter_out_13 cpsw.cpts_hw4_push
    timesync_event_introuter_out_14 cpsw.cpts_hw5_push
    timesync_event_introuter_out_15 cpsw.cpts_hw6_push
    timesync_event_introuter_out_16 cpsw.cpts_hw7_push
    timesync_event_introuter_out_17 cpsw.cpts_hw8_push
    timesync_event_introuter_out_19 epwm0_sync
    timesync_event_introuter_out_20 SYNC0_OUT pin
    timesync_event_introuter_out_21 SYNC1_OUT pin
    timesync_event_introuter_out_22 SYNC2_OUT pin
    timesync_event_introuter_out_23 SYNC3_OUT pin
    timesync_event_introuter_out_24 icss.pr1_slv_intr 7
    timesync_event_introuter_out_25 icss.pr1_slv_intr 8