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Original question:

AM6412: AM64x power up sequence parameters

AM6412: VDD_CORE ramp up relative to VDDS_DDR

Joe Paolino
Intellectual 360 points
Part Number: AM6412
Other Parts Discussed in Thread: TPS65220, AM6421

Hello,

I plan to use TPS65220 to power the AM6421, but I'd like to use a more efficient buck to produce 0.75V (VDD_CORE) directly from my main supply.  Looking at Figure 7-5 in the datasheet it appears that the VDDS_DDR (1.1V) rail can come up before or after VDD_CORE.  I'd like to use a 1.8V rail from the TPS65220 to enable my external 0.75V buck.  Buck2 (1.8V) from TPS65220 comes up in the first row in the picture below.  Please confirm whether VDD_CORE can safely come up prior to VDDS_DDR.

Thank you

  • 0
    TI__Guru*** 143879 points

    Hello Joe Paolino,

    Thank you for the query.

    Please refer to the below sections in the data sheet and be sure to follow the below requirements.

    Figure 7-5. Power-Up Sequencing

    8. VDD_CORE can be operated at 0.75V or 0.85V. When VDD_CORE is operating at 0.75V, it shall be ramped
    up prior to all 0.85V supplies as shown in this waveform.

    10.The potential applied to VDDR_CORE must never be greater than the potential applied to VDD_CORE +
    0.18V during power-up or power-down. This requires VDD_CORE to ramp up before and ramp down after
    VDDR_CORE when VDD_CORE is operating at 0.75V. VDD_CORE does not have any ramp requirements
    beyond the one defined for VDDR_CORE. VDD_CORE and VDDR_CORE are expected to be powered by
    the same source so they ramp together when VDD_CORE is operating at 0.85V.

    Figure 7-6. Power-Down Sequencing

    3. VDD_CORE when operating at 0.75V.
    5. The potential applied to VDDR_CORE must never be greater than the potential applied to VDD_CORE +
    0.18V during power-up or power-down. This requires VDD_CORE to ramp up before and ramp down after
    VDDR_CORE when VDD_CORE is operating at 0.75V. VDD_CORE does not have any ramp requirements
    beyond the one defined for VDDR_CORE. VDD_CORE and VDDR_CORE are expected to be powered by
    the same source so they ramp together when VDD_CORE is operating at 0.85V.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    Intellectual 360 points

    Thanks, Sreenivasa.  Based on the second to last sentence there: "VDD_CORE does not have any ramp requirements..." it would seem to me that it is safe for VDD_CORE to come up at the same time or slightly before VDDS_DDR (1.1).  Is that correct?

  • +1 in reply to Kallikuppa Sreenivasa
    TI__Guru*** 143879 points

    Hello Joe Paolino,

    Your comments are in line with the sequence shown in the below diagram.

    Figure 7-5. Power-Up Sequencing

    I highlighted the care abouts in the above message.

    Regards,

    Sreenivasa 

  • 0 in reply to Kallikuppa Sreenivasa
    Intellectual 360 points

    Thanks very much, Sreenivasa

  • 0 in reply to Joe Paolino
    TI__Guru*** 143879 points

    Hello Joe Paolino,

    Thank you.

    Regards,

    Sreenivasa