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[FAQ] AM6442, AM6441, AM6422, AM6421, AM6412, AM6411 Custom board hardware design – Queries regarding Crystal selection

Lavanya M R
Intellectual 1590 points
Part Number: AM6442
Other Parts Discussed in Thread: TMDS64EVM, AM3352

Hi TI Experts,

I have the below queries regarding the crystal selection.

  1. Recommended crystal frequency for MCU_OSC0
  2. Do you have recommended part numbers for Crystal? 
  3. Can you help check if NX2016SA-25MHZ-EXS00A-CS10694, CRYSTAL 25.0000MHZ 8PF SMD could be used?
  4. Do you have recommendations for MCU_OSC0 crystal selection.
  5. Could you share the crystal part number used on the EVM? 
  6. Can i use an oscillator as the clock source?
  7. Is there a real max value for crystal ESR?
  8. Is there some guidelines for the crystal circuit layout?
  9. Is there a delay requirement for the MCU_PORz after all the power supplies ramp and does the delay depend on the clock source

Let me know your thoughts.

  • +1
    TI__Intellectual 1590 points

    Hi Board designers, 

    Refer below inputs for the queries related to the MCU_OSC0 crystal selection. 

    1.Recommended crystal frequency for MCU_OSC0

    Recommended Crystal Parallel Resonance Frequency for MCU_OSC0 is 25 MHz

    2. Do you have recommended part numbers for Crystal? 

    "Note that we do not provide part number recommendations."

    The system requirements of a customer’s product need to be considered when selecting a crystal.  We do not know the operating conditions or frequency tolerance of all attached devices within their system.  The crystal requirements defined in our datasheet only address the processor requirements, but the crystal characteristics may also influence clocks that are sourced to attached devices which have their own requirements. In some cases, the attached devices may have frequency requirements that are tighter than the processor frequency requirements.

    3. Can you help check below specs and confirm this crystal specifications meets the requirements for the MCU_OSC0 Internal Oscillator Clock Source.

    The device expert and oscillator designer reviewed the crystal requirements and agree this crystal specifications meets the requirements for the HF oscillator implemented on our AM64x, AM62x and AM62Ax Sitara processors.

    4. Do you have recommendations for MCU_OSC0 crystal selection.

    Refer below sections of the device specific datasheet.

    AM64x SitaraTm Processors datasheet (Rev. E) (ti.com)

    Figure 7-17. MCU_OSC0 Crystal Implementation

    The crystal must be in the fundamental mode of operation and parallel resonant.

    Table 7-17. MCU_OSC0 Crystal Circuit Requirements summarizes the required electrical constraints.

    5. Could you share the crystal part number used on the EVM?

    TMDS64EVM

    ABM10W-25.0000MHZ-8-K1Z-T3

    25 MHz ±10ppm Crystal 8pF 50 Ohms 4-SMD, No Lead

    Do consider parasitic capacitance introduced by the PCB when determining the crystal load cap value.

    6. Can I use an oscillator as the clock source?

    Refer 7.10.4.1.2 MCU_OSC0 LVCMOS Digital Clock Source of the device-specific data sheet. Follow the recommended XO termination.

    7. Is there a real max value for crystal ESR?

    The maximum ESR recommended is 50 ohms regardless of shunt capacitance.

    8. Is there some guidelines for the crystal circuit layout?

    Refer 9.3 Clock Routing Guidelines, 9.3.1 Oscillator Routing section of the device-specific data sheet.

    9. Is there a delay requirement for the MCU_PORz after all the power supplies ramp and does the delay depend on the clock source?

    Refer to MCU_PORz Timing Requirements in the device-specific data sheet

    RST1 Hold time, MCU_PORz active (low) at Power-up after supplies valid (using external crystal circuit) is 9500000 ns
    RST2 Hold time, MCU_PORz active (low) at Power-up after supplies valid and external clock stable (using external LVCMOS clock source) 1200 ns (This does not include the external oscillator start-up time)

    Regards,

    Lavanya M R.

  • 0 in reply to Lavanya M R
    TI__Guru**** 172004 points

    Hi TI Experts,

    I have the below additional queries regarding the crystal selection.

    10. MCU_OSC0_XI/MCU_OSC0_OUT starts before VDD_CORE voltage ramps up, is this a concern
    11. Does it have any side effect when MCU_OSC0_XI clock starts before VDD_CORE voltage ramps up? What kind of conditions let MCU_OSC0_XI doesn't start until after VDD_CORE is applied?
    12. It is assumed that when a crystal connected externally has a large change in frequency due to some factor, there will be an effect on the PLL.
    13. Does the 25MHz XTAL has an oscillation margin switching function and is there need to configure registers.
    14. Do you have some recommendations on the crystal load and load capacitance matching 

    Let me know your thoughts.

  • 0 in reply to Kallikuppa Sreenivasa
    TI__Guru**** 172004 points

    Hi Board designers, 

    Refer below inputs for the queries related to the MCU_OSC0 crystal selection. 

    10. MCU_OSC0_XI/MCU_OSC0_OUT starts before VDD_CORE voltage ramps up, is this a concern

    The oscillator is working as expected. It most cases the oscillation will start shortly after its 1.8V power rail is applied, but there may be conditions where it doesn't start until after VDD_CORE is applied.

    11. Does it have any side effect when MCU_OSC0_XI clock starts before VDD_CORE voltage ramps up? What kind of conditions let MCU_OSC0_XI doesn't start until after VDD_CORE is applied?

    No side effects.

    The oscillator has registers in the VDD_CORE power domain that controls some of its operating functions. It is very unlikely the start-up will be delayed until VDD_CORE is valid, but we are being conservative by saying the oscillation will not begin until VDD_CORE is valid to ensure the product designer provides adequate time for the oscillator to start before reset is released.


    12. It is assumed that when a crystal connected externally has a large change in frequency due to some factor, there will be an effect on the PLL.

    I would like to know the effect on the PLL when the frequency changes and how each function will operate. The factors that may cause the frequency to change include initial failure, environment, and manufacturing defects.

    Ans: It is not possible for crystals to have a large change in frequency. They have a very high-Q impedance response. The impedance drops dramatically with a very small shift in frequency, which would cause the gain in the oscillator feedback path to drop such that it is not possible to maintain oscillation. So, they are either oscillating at their designed frequency are not oscillating.

    13. Does the 25MHz XTAL has an oscillation margin switching function and is there need to configure registers.

    No HFOSC0 registers are required to be changed. These registers should remain in their default state.
    Select the appropriate crystal circuit components that are compliant to the values defined in the MCU_OSC0 Crystal Circuit Requirements table.
    Read the Load Capacitance and Shunt Capacitance sections to select the appropriate crystal circuit components.

    14. Do you have some recommendations on the crystal load and load capacitance matching 

    It is recommended to match the crystal load and the load capacitance as per the data sheet recommendations. Any difference in the crystal load and the load cap capacitance selected could result in PPM variation of the clock frequency Choose crystal load as per the standard capacitance availability to ensure matching of the capacitance.

    References

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1115457/am6411-is-it-needed-to-input-the-synchronized-clock-between-am64x-and-ethernet-phy

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    TI__Guru**** 172004 points

    Hi Board designers, 

    Additional references:

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1292714/am3352-crystal-resonator-maximum-load-capacity/4907439#4907439

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/998892/am3352-crystal-osc0---parameters---esr-and-behaviors

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/331843/crystal-frequency-stability-and-tolerance-for-osc0-on-am3352

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/332473/osc0-crystal-the-max-start-up-time-on-am3352

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/921582/amic110-min-value-of-tsx-start-up-time-of-osc0-crystal-circuit

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    TI__Guru**** 172004 points

    Hi Board designers, 

    Additional references for crystal selection

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1038770/am3358-frequency-tolerance-and-frequency-stability-of-24mhz-crystal/3841749

    The accuracy of the AM335x reference clock source should be based on system level requirements. For example, you may need a 30 PPM reference clock if an AM335x timer is being used to operate something that needs this level of accuracy. 

    The 50 PPM limit was defined for AM335x because the RMII Ethernet standard requires this accuracy. The other Ethernet standards only require 100 PPM, so you may be able to back-off on this 50 PPM requirement if not using RMII. However, this depends if you have other system function that require an accuracy of 50 PPM. I would not recommend going above 100 PPM as this may begin to effect other peripheral interfaces.

    Keep in mind, a crystal has three contributions to accuracy. There is a parameter that defines initial accuracy, another parameter that defines accuracy over operating temperature, and aging parameter that defines how much the resonate frequency changes over time due to aging effects. When selecting a crystal, you must combine all of these to determine frequency accuracy across all operating conditions for the life of the product.

    Reliable start-up is also a concern with crystal selection. The max ESR of the crystal is one of the primary concerns. The AM335x oscillator may not have enough gain to reliably start oscillation if the crystal ESR is too low. Many crystal datasheets define a worst case max ESR value for the entire family of crystals rather than a specific max ESR for the crystal being selected. In most cases the higher frequency crystals in the family will have a much lower max ESR value that what is found in the datasheet. Therefore, you may need to contact the crystal manufacture and request a device specific datasheet for the crystal part number you plan to use.

    One way to confirm you have start-up margin, is by inserting a resistor in series with the selected crystal and checking for reliable start-up across all operating conditions. I suggest you begin with a resistor value that is about 5x the max ESR of the crystal. If you have start-up issues with this value you can reduce it to 3x. There is not enough gain margin if oscillation will not reliably start with a 3x resistor. You would need to select a crystal with lower ESR if you find it will not reliably start with a 3X series resistor.

    You neve said if you were using RMII and needed 50 PPM system performance. Therefore, I cannot comment how were these options align with your system requirements.

    I noticed the Digi-key description for your existing crystal, which they are selling under part number 7A-24.000MAAJ-T was cut for an 18pF load, so it must not be one of the standard options shown in the datasheet. What load did you apply to this crystal in your product? Are you willing to change load capacitor values in your product when you change crystals? How much capacitive load does you signals apply to the crystal circuit?

    I do not think a crystal cut for 18pF load was ever appropriate for AM335x. Each load capacitor would need to be approximately 33 - 36 pF to achieve a 18pF load for the crystal and the AM335x datasheet only allows load capacitors in the range of 12 - 24 pF. 

    The highest load capacitance crystal you would be able to use is 12pF to remain in the ranged defined by the AM335x datasheet.

    The AA-24.000MAHJ-T datasheet shows their standard offering is a crystal cut for a 8pF load. However, they provide an option to specify a load capacitance. I did not see an aging parameter in this datasheet, so not sure how PPM will change over time on this crystal.  It may be a viable option as long as you apply the correct load capacitance for the crystal your purchase while remaining compliant with AM335x datasheet. However, you should validate startup reliability using the method described previously to ensure ESR in not going to be a problem.

    The ECS-240-18-30-JGN-TR datasheet does not clearly show an option for buying a crystal cut for a lower capacitive load and 20 pF is too high. You may be able to use this as a viable option if they would sell you one that was cut for 10 pF.

    AM3352: Crystal OSC0 - Parameters - ESR and Behaviors

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/998892/am3352-crystal-osc0---parameters---esr-and-behaviors/3690471

    The biggest concern is not having enough gain margin to reliably start oscillation when the higher ESR crystal is combined with the other crystal circuit components and internal oscillator.

    There is a good chance you have enough gain margin if this combination of components has been used for a while without receiving any reports of the oscillator not starting.

    In most cases the actual ESR of a crystal is much smaller than the published value. This is especially true when the ESR value you are using is taken from a data sheet that covers an entire family of crystals. The max ESR value published in a crystal family data sheet is typically inflated to cover the entire range of crystals. You may be able to reach out to the crystal manufacture and request a part number specific datasheet to confirm the max ESR of your crystal.

    You can test the gain margin by placing a resistor in series with the crystal, which increases the ESR seen my the entire circuit. We typically recommend confirming reliable start of oscillation across operating conditions when the series resistor inserted increases the ESR to at least 3x the expected ESR of the crystal. 

    Load capacitor values should be selected based on the load expected by the crystal. Crystal are cut to oscillate at the specified frequency with a specific capacitive load. The frequency of oscillation will be pulled a few PPM from the specified frequency if the load you apply is not correct. Most crystal manufactures provide a service where they evaluate your product with their crystal and make recommendations if your initial component selection is not optimum. I think the fee they charge is reasonable for any high volume product where you want to be confident that you clock solution is robust.

    Regards,

    Sreenivasa