[FAQ] AM64X/AM62X: How do I route the same GPIO bank interrupts to different destination cores?

This FAQ mainly explains routing the same GPIO bank interrupts to different destination cores.

In the above example, GPIO0_37 and GPIO0_38 pins come under Bank 2, and we are trying to route the same bank interrupt to two destination cores.
Actually, the GPIO MUX Interrupt Router works like route one input to one output. But in the current situation, the same two bank  interrupt was routed to different cores, and this is not supported in AM64X or AM62X devices.
hence the SCI client error.

Solution :

How do we solve this issue?

Method 1:
1. Route the pin interrupt to one core and route the corresponding bank interrupt to the other core.

Method 2:
1. Route pin interrupts to two cores instead of Bank interrupts.

Example Codes :

Currently, to support methods 1 and 2, the system configuration does not generate code for Pin interrupts and generates code for Bank interrupts.

So, for method 1, we need to generate code for the bank interrupt from system cfg, and for the Pin interrupt, we need to update the code manually as per the below example

And for method 2, we need to update the code manually as per the below example.

Please see the attached example for GPIO Pin interrupt

Below is an example of a pin interrupt for GPIO1_43, and if you need a pin interrupt for your selected pins, then simply update the below parameter in the Sciclient_gpioIrqSet function.

    rmIrqReq.src_index              = GPIO_PUSH_BUTTON_PIN;

Make sure that interrupt number and Router output should be properly configured  .
Below links can be helpful to configure GPIO interrupt Router.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1123825/faq-am6442-how-to-configure-the-gpio-interrupt

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1230630/faq-how-to-get-started-with-resource-partitioning-tool

Example code : 

6472.empty_am64x-evm_r5fss0-0_freertos_ti-arm-clang.zip

Conclusion :

The above solution is valid in all AM64X and AM62X devices and NO RTOS and FreeRTOS.

and explained the solution for two R5F cores, and it is the same approach for all other cores.