TDA4AH-Q1: 2 PHY's different clock one Serdes

Nathan Marchosky

Part Number: TDA4AH-Q1

Is it possible to use two SGMII PHYS simultaneously connected to a single SERDES say SERDES4, but those have different bit rates (say 1Gb/s and 100Mb./s or 1Gb/s and 2.5Gb/s). In other words, is it possible to communicate to both Phys at the same time or does that require changing the clock frequency?

over 2 years ago

0 Mark L. over 2 years ago

TI__Expert 5420 points

Hello Nathan,

I believe your question is asking if reference clocks need to be changed when using different PHYs. For SERDES4, the supported interfaces are SGMII (1G) and QSGMII (5G). Both these interfaces use a reference clock of 100 MHz so the reference clock will not need to be changed when using SGMII and QSGMII simultaneously on SERDES4.

A configuration that will require two different reference clocks is SGMII and USXGMII (SERDES1 and SERDES2). Please refer to this thread: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1219195/tda4vh-q1-sgmii-1g-and-usxgmii-10g-on-same-serdes.

From TDA4AH TRM:

Please let me know if I can clarify further.

Regards,
Mark

0 Nathan Marchosky over 2 years ago in reply to Mark L.

Prodigy 30 points

Hi Mark,

I think that helps. I looked through the table in the TRM and couldn't find any lanes supporting XAUI, do you know which lanes on which SERDES support XAUI?

0 Mark L. over 2 years ago in reply to Nathan Marchosky

TI__Expert 5420 points

Hello again,

Thank you for bringing that to my attention. I found this from the datasheet:

XAUI is the same as 2.5G SGMII.

Regards,
Mark

0 Nathan Marchosky over 2 years ago in reply to Mark L.

Prodigy 30 points

Okay so to clarify if I use 2.5Gb SGMII/XAUI on one of the Serdes 4 lane I can't use 1Gb SGMII on the same Serdes simultaneously without changing the reference clock from 156.25MHz to 100MHz?

0 ShreyasRao over 2 years ago in reply to Nathan Marchosky

TI__Guru 62550 points

Hi Nathan,

In this device, there is dual internal ref clk support. That means that you can have SGMII on lanes 0 and 1 with 100MHz clk, and lanes 2 and 3 running XAUI at 156.25MHz ref clk. and the current SDK has support existing for the XAUI + SGMII use case.

Hope this clarifies, please let me know if you have any questions.

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TDA4AH-Q1: 2 PHY's different clock one Serdes