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[FAQ] What is a PRU core? Why are PRU GPIO signals different from regular GPIOs?

What is the PRU core? Why is it useful for applications that would typically require an FPGA or a CPLD to work?

INTRODUCTION

Many systems need to interface to an external device that does not use a standard protocol. These external devices can range from an array of analog to digital converters (ADCs) to a peripheral with a proprietary bus interface. TI’s Sitara processors with programmable real-time unit (PRU) cores are designed to communicate with these devices without the need to add FPGAs, ASICs, CPLDs, etc to the design.

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This FAQ applies to all Sitara processors with a PRU subsystem, including AM243x, AM263x, AM335x, AM437x, AM57x, AM62x, AM64x, AM65x. For more information about the PRU, reference the PRU Development section of the Sitara multicore development and documentation FAQ.

  • ALTERNATIVES TO THE PRU

     Designers typically add a field programmable gate array (FPGA) or custom programmable logic device (CPLD) to the system if their design needs nonstandard communication with an external device. However, adding FPGAs increases cost and complexity to the design. Adding additional chips to the design also increases the possibility of the product getting impacted by supply chain issues that result in long lead times.

    Another approach is to use the microcontroller (MCU) itself to interface with the external device. An MCU without flexible external logic uses software to control the external device via its general purpose input/output (GPIO). However, there are fundamental drawbacks to using a CPU core (like an Arm Cortex M or RISC-V) to manipulate GPIO pins. Chip infrastructure like a Network On Chip (NOC) exists between the CPU cores and the GPIO pins (i.e., there is no “direct connection” to GPIOs). The CPU core may have a pipeline. These and other factors mean that compared to an FPGA, a standard MCU will have increased latency and lower determinism (i.e., higher signal jitter) when interacting with a GPIO.

    Let's say you just need to drive some outputs with a certain waveform. In that case, software performs back to back writes to create the desired pattern on the SOC pins. The pattern is written from the CPU’s internal registers through the NOC infrastructure to reach the GPIO. The NOC can add tens to even hundreds of nanoseconds of latency and jitter to the GPIO write commands. As a result, the system might not meet the peripheral’s timing requirements for the output signal duty cycle, the relationship between outputs, etc.

    Another typical need for these custom interfaces is a request / acknowledge. For example, the output data or command sent by the CPU is triggered by an input command or data coming from the peripheral. CPU read / write interactions have 2x the latency, because of the round trip delay to read the input from the GPIO, process the input, and then write an output back to the GPIO.

  • TI’S PRU SOLUTION

     TI’s PRU core is a best-in-class custom CPU designed to have the lowest latency and highest determinism in GPIO reads & writes. Like many other CPU cores, the PRU has 32 32-bit registers inside the core. However, two of these registers are dedicated for GPIO functionality. One register is directly connected to general purpose output (GPO) signals. GPO signals are toggled by writing to the register. The other register is directly connected to general purpose input (GPI) signals. GPI signals are read by reading the register.

    Since there is no NOC circuitry between the registers and the pins, signal latency from the core to the processor pins is dramatically reduced. Output signal jitter due to the signal path is 100% removed. The PRU gives best in class performance without losing flexibility.

    Input signal performance is improved as well. The PRU has commands to stall the program until a GPI event occurs. This gives best case latency to produce an output response after observing a trigger on an input. Since the GPI/GPO registers are embedded within the PRU, the PRU allows for perfectly deterministic timing relationships between single inputs and outputs, as well as between multiple input signals or multiple output signals.