Above is the privious question I asked for help, I'd like to Thank Shankari G[https://e2e.ti.com/members/6681393] first.
To talk about the reason of the question, here is my analysis process:
- I first doubted if it had something to do with MPAX, because the question seams that both 0x8000_0000 and 0xA000_0000 are mapped to the same phy address. So I checked the MPAX configuration registers(XMPAXL/XMPAH), and which are right according the Corepac User Guide(SPRUGW0C);
- Then I rebuild the Platform, and configured the DDR range: 0x8000_0000~0xFFFF_FFFF, size: 2GB. but not worked.
- At last, I checked the DDR configurations, I found something in SPRUHN7C-SDCFG, which is the SDRAM Configuration register. In SDCFG, the "NM" fields (DDR3 data bus width) is the KEY point, which must be set according the DDR storage particles.
Here is my board info:
DSP model: TMS320C6678
DDR3: DDR3 is connected to 4Gb/4bit DDR16 surface-mount memory particles, designed as a single rank
In my previous project, the DDR SDCFG like this:
TEMP = 0;
TEMP |= 0x3 << 29; // SDRAM_TYPE bit field 31:29 (fixed value) DDR3 ok
TEMP |= 0x0 << 27; // IBANK_POS bit field 28:27 8banks ok
TEMP |= 0x3 << 24; // DDR_TERM bit field 26:24 RZQ/6Ω
TEMP |= 0x0 << 21; // DYN_ODT bit field 22:21 Disable
TEMP |= 0x1 << 18; // SDRAM_DRIVE bit field 19:18 RZQ/7Ω
TEMP |= 0x2 << 16; // CWL 7clocks
TEMP |= 0x2 << 14; // NM bit field 15:14, 0X2:16bits width
TEMP |= 0xA << 10; // CL 9clock
TEMP |= 0x7 << 7; // ROWSIZE bit field 9:7 16 row bits ok
TEMP |= 0x3 << 4; // IBANK bit field 6:4 8 banks ok
TEMP |= 0x0 << 3; // EBANK bit field 3:3 DCE0# ok
TEMP |= 0x2; // PAGESIZE bit field 2:0 1024-word page, 10 column bits
DDR_SDCFG = TEMP;
The Field[15:14] is set to 0x2(16-bit bus width), which is not matched my board , So I set the field to 0x0(64-bit bus width).
Then it worked!
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