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[FAQ] AM6442, AM6441, AM6422, AM6421, AM6412, AM6411 Custom board hardware design – USB2.0 interface

Lavanya M R
Intellectual 1590 points
Part Number: AM6442
Other Parts Discussed in Thread: TMDS243EVM, TMDS243DC01EVM, TMDS64DC01EVM, LP-AM243, BP-AM2BLDCSERVO, BOOSTXL-IOLINKM-8

Hi TI Experts,

I have the below queries regarding implementation of USB interface

1. Supported USB interface configuration

2. Is VBUS connection required for Host configuration or Device configuration

3.  Can I have the VBUS supply input connected when the SoC power supply is switched off

4. Is there a power sequencing requirement for VBUS 

5. Can I connect 5V input from the USB connector directly to VBUS 

6. Recommended VBUS supply voltage divider 

7. SOC VBUS input voltage range and Zener diode connection 

8. Supported USB Backup bootmode configuration. 

9. Recommended USB RCALIB resistor 

10. How to deal with the USB unused pins 

11. Is the USB0_ID connection required for Host configuration or Device configuration.  

12. Power supply switching and protection when the SOC is configured as USB Host

13. Are these recommendations valid for other Sitara processors or MCUs? 

14. Do you have some recommendations on the Type-C implementation.

15. Can I use 3.4K instead of 3.5K.

16. Do the differential signal pins (USB, etc.) have the capabilities to adjust the swing of the voltage?

Let me know your thoughts.

  • +1
    TI__Intellectual 1590 points

    Hi Board designers, 

    1. Supported USB interface configuration. 

    USB0 interface supports Host or Device or Dual-Role (DRD)

    1. Is the VBUS connection required for Host configuration or Device configuration.

    VBUS connection for Host interface is optional.

    It is recommended to connect the VBUS when the USB interface is configured as Device.

    The recommended voltage range is the divided voltage equivalent of 4.75 V - 5.25 V for normal operation.  

    1. Can I have the VBUS supply input connected when the SoC power supply is switched off

    USB VBUS IO is fail-safe. The VBUS input does not have any dependency on the SOC power supply.

    1. Is there a power sequencing requirement for VBUS input. 

    USB VBUS IO is fail-safe and do not have any sequencing requirements.

    1. Can I connect 5 V input from the USB connector directly to VBUS input. 

    VBUS pin cannot be connected directly to external/connector VBUS, as IO is not 5 V compliant. Recommend using voltage divider and/or current limiter to ensure IO requirements are met. VBUS pin can be consider fail-safe only if recommended external divider circuit is used.

    Connection of 3.3 V directly to VBUS input is not allowed or recommended.

    For USB Device interface, it is recommended to connect a switched external USB VBUS supply to the USB0_VBUS input of the SOC through recommended resistor divider.

    1. Recommended VBUS supply voltage divider 

    Refer section 9.2.3 USB VBUS Design Guidelines of the data sheet.

    1. SOC VBUS input voltage range and Zener diode connection 

    We do not define VBUS thresholds. VBUS thresholds are defined in the USB specification. The thresholds were designed to be compliant to the USB specifications and validated via USB-IF compliance tests.
    The VBUS input has an ESD clamp to the 3.3 V rail. The USB VBUS Design Guidelines section of the datasheet defines the VBUS connection topology. This voltage divider / clamp circuit allows VBUS to go up to 30 V without harming the VBUS input. The Zener diode could be removed and a 20 KΩ resistor could be substituted for the 16.5 KΩ and 3.5 KΩ resistors if your system will never apply a VBUS potential greater than 5.5 V and the 5.5 V is sourced on-board.

    1. Supported USB Backup bootmode configuration.

    USB0 interface is recommended to be configured as a device. USB DFU backup mode works with 0.75 V SOC core supply.

    1. Recommended USB RCALIB resistor 

    Refer below section of the data sheet. 

    6.3.25 USB, 6.3.25.1 MAIN Domain, Table 6-79. USB0 Signal Descriptions

    RCALIB resistor should not exceed ±1% at any operating condition for the lifetime of the product.

    1. How to deal with the USB unused pins 

    Refer below section of the data sheet. 

    6.4 Pin Connectivity Requirements, Table 6-80. Connectivity Requirements 

    1. Is the USB0_ID connection required for Host configuration or Device configuration. 

    It is recommended to connect USB0_ID pin to VSS through a 0 Ω resistor when the USB interface is configured as Host.

    It is recommended to leave the USB0_ID pin floating when the USB interface is configured as Device.

    For implementations that do require DRD functionality, connect USB0_ID pin directly to the corresponding ID pin on a USB Micro-AB connector. Depending on the cable attached, the USB0_ID pin will be terminated, and the processor will be configured as Host or Device.

    1. Power supply switching and protection when the SOC is configured as USB Host

    USB0_DRVVBUS can be used to control the power (load) switch. The USB interface or the Linux driver is not checking the status of VBUS to determine if there is a fault condition. In that case, you should connect the fault output of the VBUS power (load) switch to a GPIO and configure the GPIO to generate an interrupt that indicates there has been an over-current condition.

    1. Are these recommendations valid for other Sitara processors or MCUs?

    The recommendations are valid for the following family of devices:

    AM243x

    1. Do you have some recommendations on the Type-C implementation.

      AM64x EVM or SK does not have the implementation.

      Refer below starter kit for implementation.

      https://www.ti.com/tool/SK-AM62B-P1

    2. Can I use 3.4K instead of 3.5K.

    It should be Ok to use a 3.4K for the divider. It is recommended to select 3.48K value based on the availability.

    16. Do the differential signal pins (USB, etc.) have the capabilities to adjust the swing of the voltage?

    No.

    Note: 

    Ensure the recommended capacitors are provided for the VBUS supply near to the connector (Host > 120 uF and Device (1-10 uF))

    USB0_DRVVBUS has an internal pulldown enabled by default.

    Refer below documents during the USB interface design.

    Recommended References for review and design of custom board
    AM64x
    Data sheet
    AM64x Sitara Processors datasheet
    www.ti.com/.../sprsp56
    Hardware Design Guide
    www.ti.com/.../sprad67
    Schematic Design and Review Checklist for AM64x
    www.ti.com/.../spracu5
    DDR Board Design and Layout Guidelines
    www.ti.com/.../spracu1
    DDR Board Design and Layout Guidelines
    www.ti.com/.../sprad06
    Errata
    https://www.ti.com/lit/pdf/sprz457

    AM243x

    Data sheet
    AM243x SitaraTm Microcontrollers datasheet 
    www.ti.com/.../sprsp65


    Hardware Design Guide
    www.ti.com/.../sprad67
    Schematic Design and Review Checklist for AM64x
    www.ti.com/.../spracu5
    DDR Board Design and Layout Guidelines
    www.ti.com/.../spracu1
    DDR Board Design and Layout Guidelines (AM62x)
    www.ti.com/.../sprad06
    Errata AM64x/AM243x Processor Silicon Revision 1.0, 2.0
    www.ti.com/.../sprz457

    EVM for ALV package
    TMDS243EVM AM243x evaluation module for Arm® Cortex®-R5F-based MCUs
    www.ti.com/.../TMDS243EVM
    Design files


    www.ti.com/.../sprr465
    TMDS243DC01EVM
    AM243x and AM64x evaluation module breakout board for high-speed expansion
    www.ti.com/.../TMDS243DC01EVM
    www.ti.com/.../sprr443

    TMDS64DC01EVM AM64x IO-link and high-speed breakout card
    www.ti.com/.../TMDS64DC01EVM
    dr-download.ti.com/.../sprr457.zip

    Launchpad for ALX package
    LP-AM243 AM243x general purpose LaunchPadTm development kit for Arm®-based MCU
    www.ti.com/.../LP-AM243
    www.ti.com/.../sprr433

    BP-AM2BLDCSERVO
    AM2x Brushless-DC (BLDC) Servo Motor BoosterPack
    www.ti.com/.../BP-AM2BLDCSERVO
    www.ti.com/.../sbar023

    BOOSTXL-IOLINKM-8 Eight port IO-Link master BoosterPack
    www.ti.com/.../BOOSTXL-IOLINKM-8

    Regards,

    Lavanya M R.

  • 0 in reply to Lavanya M R
    TI__Guru**** 172604 points

    Hi Board designers, 

    Additional inputs regarding USB RCALIB resistor implementation:

    The IP specification TI received from the USB PHY design team defined a 500 ohm +/-1% calibration resistor. A few weeks ago another customer reminded us 500 ohms is not a standard value for 1% resistors. They were having problems sourcing a 500 ohm +/-1%, so asked if the could use a 499 ohm +/-1% resistor.

    I ask the USB PHY team if we could change the recommendation from 500 ohm +/-1% to 499 ohm +/-1% to make resistor selection easier for our customers. They confirmed this would be okay, so we changed the recommendation in the datasheet.

    I assume your board has two 1 kohm +/-1% resistors connected in parallel, and you are asking if this will be okay. This should be okay since the USB PHY was initially designed for a 500 ohm +/-1% resistor.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    TI__Guru**** 172604 points

    Hi Board designers, 

    Refer below section of the TRM for information related to USB2 polarity revu

    • USB2 PHY:
    – Fully compliant with UTMI+ Level 3 specification revision 1.0
    – Supports high-speed (480 Mbps), full-speed (12 Mbps) and low-speed (1.5 Mbps) data rates
    – Supports battery charging BC1.2v specification
    – Supports host, peripherals and OTG 2.0 (dual role device) applications
    – Supports D+/D- lane reversal for flexible board integration
    – Supports USB low-power states; namely, suspend and link power management (LPM)
    – Supports internal comparators for monitoring OTG voltage thresholds
    – Supports multiple PLL reference clocks
    – Supports internal PLL for high-speed (480 MHz) clock and data recovery (CDR) operation
    – Integrated termination resistors (45 Ω, 1.5 KΩ, and 15 KΩ)
    – Supports built-in self-test (BIST) for production testing
    – 3.3-V ESD support on VBUS

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    TI__Guru**** 172604 points

    Hi Board designers, 

    Refer below explanation for connecting the USB interface signals directly:

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/261717/am335x-series-resistors-on-usb_dp-usb_dm/914980?tisearch=e2e-sitesearch&keymatch=userdisplayname%25253A%252522Peaves%252522%252520%252526%252526%252520reflection#914980

    According to the schematic checklist (processors.wiki.ti.com/.../AM335x_Schematic_Checklist of AM335x,

    "USBx_DP and USB_DM should never have any series resistors or capacitance on these signals. These signals should be straight traces to the connector with no stubs or test points."

    Can I know the reason why?


    (observed problem)

    * when connected 10 ohm series resistors (for avoiding ESD problem), error happened (at the driver) while transferring data through USB port

    * when replacing it with 0 ohm, the error does not happen

    * when comparing Eye-Patterns, there is no big difference (both meet the specification)


    The additional 10 ohms of resistance creates an impedance mismatch in the transmission line.

    This impedance mismatch causes a portion of the energy in the waveform propagating down the transmission line to be reflected. The reflection will be combined with data patterns propagating down the transmission line with the result being certain data patterns distorted beyond recognition. Some data patterns may be affected more than others due to many variables related to these reflections. It is possible the standard test packet may not be significantly affected by this impedance mismatch.

    It is very important to maintain a 90 ohm differential transmission line to prevent any reflections.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    TI__Guru**** 172604 points

    Hi Board designers, 

    Inputs related to USBx_VBUS voltage 

    My customer wants to know (1) the USB0_VBUS input pin detect HI_min and LOW_max thresholds, as well as (2) how over-voltage clamping occurs on that pin;
    It is said that the buffer is powered by three domains (0.85V/1.8V/3.3V) and probably only one is attached to the 'substrate clamp diode'?
    Also (3), what would the allowed max clamp current be, non-destructive, via the substrate, either with or without power to the CPU?

    We do not define VBUS thresholds. VBUS thresholds are defined in the USB specification. The thresholds were designed to be compliant to the USB specifications and validated via USB-IF compliance tests. 

    The VBUS input has an ESD clamp to the 3.3V rail. The USB VBUS Design Guidelines section of the AM64x datasheet defines the VBUS connection topology. This voltage divider / clamp circuit allows VBUS to go up to 30V without harming the VBUS input. The Zener diode could be removed and a 20 kohm resistor could be substituted for the 16.5 kohm and 3.3.48 kohm resistors if your system will never apply a VBUS potential greater than 5.5V.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    TI__Guru**** 172604 points

    Hi Board designers, 

    Inputs related to use of Common Mode Choke

    Page 11

    USB3.0 USB2 common mode filter ACM2012-900-2P-T002

    Common-mode chokes may be needed for EMI/EMC control. Note that these may reduce the signal amplitude and degrade performance.

    https://www.ti.com.cn/cn/lit/an/sprack7b/sprack7b.pdf

    https://www.ti.com/lit/an/sprabt8a/sprabt8a.pdf

    Regards,

    Sreenivasa