AM625: OLDI voltage swing and rise/fall time

Hello Prema

Thank you for the query.

Please verify the waveform with respect to the below spec.

Can you please confirm if the OLDI is functional.

Regards,

Sreenivasa

Hi Sreenivasa,

The OLDI is functional. The LCD display is working. 

However these are the voltage readings we are measuring for OLDI CLK, data(refer screenshot below).

We are probing these signals on the LCD. the voltage values are not within 250 - 400 mv , also rise and fall time (max 0.5ns) as per datasheet

Clk: pls refer to the min, max ,top, base values

data:

pls let us know if this is of concern. 

Regards

Prema

Hello Prema, 

Thank you.

Premalatha Royappan said:

We are probing these signals on the LCD.

Help Me understand what you mean by LCD - is it on the carrier board or the LCD board.

Do you have any filters on the OLDI signals?

Regards,

Sreenivasa

Hi Sreenivasa,

We have not mounted any filters on OLDI interface. However,we have provided esd diodes. Below is a snapshot from our schematics. 

By saying 'probing on LCD' , we meant the signals were probed at the LCD board which would be the final destination point for the OLDI signals.

Hello Prema, 

Thank you for the explanation.

Let me review and update you.

Regards,

Sreenivasa

Prema,

Can you double check on how you are calculating rise/fall times? Unlike with single ended TTL/LVTTL/LVCMOS signals, where rise/fall time is measure from 10% to 90% magnitude, LVDS rise/fall times are typically measured from 20% to 80% magnitude.

If I look at your plots under the 20%/80% constraint, visually, it looks to me to be pretty close to the 0.5ns target.

Thanks,

Stuart

Hi Stuart,

We will share the captures with 100 ohms load after checking with LCD vendor, as discussed in call. I'm attaching the LCD datasheet here for your reference.

LCD185-101CTL1AGNTTR0.1_DS-R1.1.pdf

Hello Prema, 

Thank you for the inputs and looking forward to the measurements.

Regards,

Sreenivasa

Hi Sreenivasa,

We recaptured signals w.r.t OLDI.

We mounted 100 ohms differential load near the connector and verified the signals. The signals are now as per the OLDI characteristics provided in the processor datasheet. The voltage levels are above 250mV and Rise time/fall time measured manually (20% and 80%) using cursors and found to be within 500 ps. Following are the captures.

Hello Prema, 

Thank you for the inputs.

I guess the timing are measured with the far end differential termination enabled.

I am verifying internally with the experts if they have additonal thoughts.

Regards,

Sreenivasa

Hello Prema, 

Please refer to the below section of the data sheet

7.11.5.17 OLDI
7.11.5.17.1 OLDI0 Switching Characteristics
Table 7-110 and Figure 7-94 present switching characteristics for OLDI0.
Table 7-110. OLDI0 Switching Characteristics

(1) Slow mode: TXDRV[3:0] = 0100b without back termination (RTERM_EN = 0b with 100Ω differential termination on far-end only)
(2) Fast mode: TXDRV[3:0] = 1000b with back termination (RTERM_EN = 1b with 100Ω differential termination on far-end only, or
RTERM_EN = 0b with 100Ω differential termination on near-end and far-end)

Could you help me understand the setting you are using.

Did you have a chance to measure the waveforms near to the SoC pins without the terminations connected to the OLDI display?

Regards,

Sreenivasa

Hi Sreenivasa

The oldi register settings are the default values which corresponds to option 1(slow mode with 100 ohm differential termination on far end).

We measured the oldi signals near the processor without termination,but they are not ok.

With 100 ohms load at the LCD connector (without connecting LCD) we are seeing proper signals, which are meeting the DC specs as per processor datasheet. We are hence closing on this issue. Pls correct us in case of any concerns.