Hi TI experts,
My customer provided a TDA4VE UART log. They only use DDRSS0 LPDDR4 4GB. log shows DDR test fail.
1. I want to know if DDR training has been done before DDR test? Or does it use the most original parameter configuration?
2.FAILURE (read/write[hhw]) @ 0xdfff7e40: expected 0x17ffdf91, actual 0xe806df91)
FAILURE (read/write[hhw]) @ 0xdfff7e44: expected 0x17ffdf92, actual 0xe806df92)
In this log, a line of failure data has a physical address and 32 bit data. It looks like the previous 16 bit data has bitflip( expected and actual do not match), seems reading another wrong data.
One DDR data bus width is 32 bit two-channel. Does this 32 bit data mean DDR data bus width? So the first 16 bit data is channel 0 or 1?
Or is there another way to decode DDR physical addresses and data? Or can you see some failure information from this log?
Thanks~
U-Boot SPL 2021.01 (Oct 07 2023 - 18:55:28 +0800) ti_sci system-controller@44083000: Message not acknowledgedSYSFW ABI: 3.1 (firmware rev 0x0008 '8.6.3--v08.06.03 (Chill Capybar') EEPROM not available at 0x50, trying to read at 0x51 Reading on-board EEPROM at 0x51 failed 1 k3_ddrss_ofdata_to_priv(dev=41c67284) k3_ddrss_power_on(ddrss=41c6d568) LPDDR4_Probe: PASS LPDDR4_Init pd: PASS LPDDR4_Init: PASS [hhw] OK: LPDDR4_HardwareRegInit PASS!! LPDDR4_StartTest readreg: PASS ------------------------------------------------------------- hhwtest: ddrss->ddr_freq0 = 27500000 hhwtest: ddrss->ddr_freq1 = 1066500000 hhwtest: ddrss->ddr_freq2 = 1066500000 ------------------------------------------------------------- [hhw] k3_lpddr4_freq_update: received freq change req: req type = 1, req no. = 0 , instance = 0 [hhw] k3_lpddr4_freq_update: received freq change req: req type = 0, req no. = 1 , instance = 0 [hhw] k3_lpddr4_freq_update: received freq change req: req type = 1, req no. = 2 , instance = 0 [hhw] k3_lpddr4_freq_update: received freq change req: req type = 0, req no. = 3 , instance = 0 [hhw] k3_lpddr4_freq_update: received freq change req: req type = 1, req no. = 4 , instance = 0 LPDDR4_StartTest start: PASS LPDDR4_Start readreg: PASS /********************************************************************/ /************************ DDR TEST ************************/ /********************************************************************/ DRAM: 0x080000000 DRAM: 0x80000000 ~ 0xf0000000 Testing: 0x80000000 ~ 0xf0000000 Iteration: 1 ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ..... FAILURE (read/write[hhw]) @ 0xdfff7e40: expected 0x17ffdf91, actual 0xe806df91) FAILURE (read/write[hhw]) @ 0xdfff7e44: expected 0x17ffdf92, actual 0xe806df92) FAILURE (read/write[hhw]) @ 0xdfff7e48: expected 0x17ffdf93, actual 0xe806df93) FAILURE (read/write[hhw]) @ 0xdfff7e4c: expected 0x17ffdf94, actual 0xe806df94) FAILURE (read/write[hhw]) @ 0xdfff7e50: expected 0x17ffdf95, actual 0xe806df95) FAILURE (read/write[hhw]) @ 0xdfff7e54: expected 0x17ffdf96, actual 0xe806df96) FAILURE (read/write[hhw]) @ 0xdfff7e58: expected 0x17ffdf97, actual 0xe806df97) FAILURE (read/write[hhw]) @ 0xdfff7e5c: expected 0x17ffdf98, actual 0xe806df98) ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ................................................................ ..................... FAILURE (read//write[hhw]): @ 0xdfe67e40: expected 0xe806606e, actual 0x17f9606e) FAILURE (read//write[hhw]): @ 0xdfe67e44: expected 0xe806606d, actual 0x17f9606d) FAILURE (read//write[hhw]): @ 0xdfe67e48: expected 0xe806606c, actual 0x17f9606c) FAILURE (read//write[hhw]): @ 0xdfe67e4c: expected 0xe806606b, actual 0x17f9606b) FAILURE (read//write[hhw]): @ 0xdfe67e50: expected 0xe806606a, actual 0x17f9606a) FAILURE (read//write[hhw]): @ 0xdfe67e54: expected 0xe8066069, actual 0x17f96069) FAILURE (read//write[hhw]): @ 0xdfe67e58: expected 0xe8066068, actual 0x17f96068) FAILURE (read//write[hhw]): @ 0xdfe67e5c: expected 0xe8066067, actual 0x17f96067) ................................................................ ................................................................ ........................................SPL initial stack usage: 13472 bytes Trying to boot from MMC2 Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted Starting ATF on ARM64 core... NOTICE: BL31: v2.8(release):v2.8-226-g2fcd408bb3-dirty NOTICE: BL31: Built : 17:56:46, Mar 1 2023