This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320DM648: The effect of changing crystal oscillators with different jitter values.

Part Number: TMS320DM648


Our customers have two questions.

1. verification of the cause of the problem and how to correct it in the equipment where the problem occurred in the LAN communication.
2. verification on another device that did not experience the problem despite similar changes (they are happy not to have to fix 1).

Background information below.

They are making a device using TMS320DM648, but when they changed some parts, they can no longer communicate over Ethernet.
The change was made to the crystal, which used to supply clocks to CLKIN1/2, REFCLKp/n and PHY independently. Initially, a 40ps jitter was used, but the problem occurred when the jitter was changed to 80ps.
They eventually put the crystals back in, and they found the cause of this in the datasheet, where the jitter limit was 100ps for CLKIN1/2 but 50ps for REFCLKp/n. Is it safe to assume that this fault is due to the difference in these limits?

The reason for this question is that there is another mass-produced machine, where 80 ps crystals were already used. Hundreds of units have already been produced and this has not been a problem.
If the earlier problem was caused by jitter, why do you think the problem did not occur with this equipment? The circuit is a little different, in the equipment in mass production, the CLKIN1/2, REFCLKp/n and PHY clocks are divided and supplied from a single crystal. We would like to confirm that this crystal does not need to be changed to 40ps as well.

Best Regards,

Kouji Nishigata

  • Any parameter that is outside the device specification could result in an issue, either immediately, or later.   Specifically for the Ethernet interface, the datasheet has the following note related to REFCLKP/N:

    Jitter on the reference clock will degrade both the transmit eye and receiver jitter tolerance thereby
    impairing system performance. A good quality, low jitter reference clock is necessary to achieve
    compliance with most if not all physical layer standards (see Table 6-83).

    All silicon devices have some variance on process, this could be why the initial batch of boards saw no issue. However, there could still be a the possibility of an issue occurring in the future due to aging.