Hi Expert,
TI spl init sequence:
...
sdram_init(); // write ddr parameter into register
//read/write ddr3 to verify ddr3 size,but some ddr3 will fail at this step when mass production,
//read back value is not same as write value,
//ram_size= 16Byte,but but actually it is 128MB
gd->ram_size = get_ram_size(...);
...
Wrong ram size will eventually cause the stack to be placed on an illegal address and data abort will occur.
However, the problem can be avoided by adding a delay of at least 15us between these two lines, as follows:
...
sdram_init();
udelay(15);
gd->ram_size = get_ram_size(...);
...
Do you have any idea why this 15us delay is needed?
Thanks
Daniel