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AM3352: AM3352+DDR3 will boot fail sometimes

Part Number: AM3352

Hi Expert,

TI spl init sequence:

sdram_init(); // write ddr parameter into register 

//read/write ddr3 to verify ddr3 size,but some ddr3 will fail at this step when mass production,

//read back value is not same as write value,

//ram_size= 16Byte,but but actually it is 128MB 
gd->ram_size = get_ram_size(...);

Wrong ram size will eventually cause the stack to be placed on an illegal address and data abort will occur.

However, the problem can be avoided by adding a delay of at least 15us between these two lines, as follows:

gd->ram_size = get_ram_size(...); 

Do you have any idea why this 15us delay is needed?



  • Not sure why that would be needed.  The sdram_init function should complete all of the DDR initialization before it exits so subsequent code can access the DDR3.  Has uboot been altered in any way?  

    It is possible that a poor input clock could change the timing of sdram_init.  

    Also, sdram_init() detecting the correct memory?  there is a call to emif_sdram_type() in the function