Other Parts Discussed in Thread: DRA829,
How to generate a PPS signal from J7 devices?
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
J7 devices have CPTS Module for TimeSync with External Network using gPTP protocol and have support for software stack in RTOS SDK. Soc also have a capability for generation of PPS Signal with desired time interval.
The gPTP stack in SDK version below 9.0 is for testing purpose only, not for production support.
In Order to generate PPS signal we have use GenF in CPTS and which needs to be routed to SYNCx_OUT pins for outputting the PPS signal on Pins.
In order to get PPS signal with time sync clock, we need to adjust GenF PPM similar to CPTS PPM during gPTP time sync adjustment.
For enabling the GenF we have to follow sequence mentioned below
1. Make sure Length value is 0 (set to 0 before configuration of Compare Low & High registers)
2. Configure compare High register first followed by compare Low register.
3. Configure Genf control register for polarity if required.
4. Configure the Length register.
CPTS time should be lower than the value written in GenF compare registers.
Above configuration will generate GenF signal. In order to get PPS signal on pins (need to configure the Pin Mux corresponding to SYNCx_OUT), we need map the GenF to Syncx_OUT which is by configuring the TIMESYNC_INTRTR0_OUTL_xx to TIMESYNC_INTRTR0_IN_yy.
TIMESYNC_INTRTR0_OUTL_34 (SYNC0_OUT) to TIMESYNC_INTRTR0_IN_14 (CPSW0_CPTS_GENF0_0)
Which by setting TIMESYNC_INTRTR0_MUXCNTL_y Register (00A4 0004h + 4*34) [i.e. SYNC0_OUT out], with value of 0xE [i.e. CPSW0_CPTS_GENF0_0 Input].
Please refer to below register description for more details.
Configure the router before configuring the GenF.
Please refer to above attached patches as reference for PPS (1Hz) signal generation in J721E/DRA829/TDA4VM.
Please refer to below patch for PPS support on MCU CPSW CPTS.
In above PPS patch, GENF_1 signal is mapped to HW4_PUSH to print timestamp on every PPS signal, this is how it is validated on Linux SDK.
In order to generate PPS signal on Pin, need to map GENF_1 to any of SYNCn_OUT (34 to 37 TimeSync router OUT) pin, so that you can capture the PPS signal.
Note that need to enable (select pin mux) the pin corresponding to syncn_out refer to TD for Pin details.