[FAQ] AM625SIP Custom board hardware design – Collaterals to Get started

Hi Board designers, 

The below links are a quick reference to the collaterals that can be referred when starting a custom design.

Device Selection and features

Product Page

https://www.ti.com/product/AM625SIP

Datasheet

AM625SIP – AM6254 Sitara Processor with Integrated LPDDR4 SDRAM datasheet

https://www.ti.com/lit/pdf/sprsp98

AM62x Sitara Processors datasheet

https://www.ti.com/lit/pdf/sprsp58

Silicon Errata

AM62x Processor Silicon Revision 1.0

https://www.ti.com/lit/pdf/sprz487

Technical Reference Manual

AM62x Sitara Processors Technical Reference Manual

https://www.ti.com/lit/pdf/spruiv7

Custom Board design:

Hardware Design Considerations

Hardware Design Considerations for Custom Board Using AM625, AM623, AM625SIP, AM625-Q1, AM620-Q1 Family of Processors

https://www.ti.com/lit/pdf/sprad05

Schematic Design and Review Checklist

AM62x Processor Family (Recommended)

AM623, AM625, AM625SIP, AM620-Q1, AM625-Q1 Processor Family Schematic Design Guidelines and Schematic Review Checklist

https://www.ti.com/lit/pdf/sprado3

AM62X processor families (For references) 

AM62x, AM62Ax, AM62D-Q1 and AM62Px Processor Families Schematic, Design Guidelines and Review Checklist

https://www.ti.com/lit/pdf/sprad21

Power Consumption

AM62x Maximum Current Ratings

https://www.ti.com/lit/pdf/sprada6

Enabling Low Power Embedded Systems With AM62x Processors
https://www.ti.com/lit/wp/sprad41/sprad41.pdf

AM62x Power Consumption
https://www.ti.com/lit/an/spradg1/spradg1.pdf

AM62x Power Estimation Tool

https://www.ti.com/lit/pdf/sprad31

AM62x Power Consumption

https://www.ti.com/lit/pdf/spradg1

SoC power solutions Application notes:

Powering the AM625SIP With the TPS65219 PMIC

https://www.ti.com/lit/pdf/slvafp8

Evaluation - EVM

SK-AM62-SIP Design Package Folder and Files List
www.ti.com/.../SK-AM62-SIP
https://www.ti.com/lit/pdf/sprt785

SK-AM62-SIP Design File Package

https://www.ti.com/lit/zip/sprr482

>ALG file converted to .PCBDOC

.ALG file 

PROC162E1_BRD1_alg.zip

Altium file generated from .ALG

PROC162E1_BRD_altium.zip

SK-AM62-LP Design Package Content Overview
www.ti.com/.../SK-AM62-LP
www.ti.com/.../sprt778
Design File Package
https://www.ti.com/lit/zip/sprr471

SK-AM62B-P1 Design Package Content Overview (Rev. A)
www.ti.com/.../SK-AM62B-P1
www.ti.com/.../sprt777
Design File Package
www.ti.com/.../spar001

Schematics (Reference) for RMII interface 

PROC135E1_SCH.pdf

PROC156E1_SCH.pdf

RMII_Length_Matching.xlsx

Note:  We did functionally validate the common clock configuration. No other clocking options were tested. 

Ethernet PHY daughter card 
https://www.ti.com/tool/DP83867-EVM-AM

https://www.ti.com/tool/DP83826-EVM-AM2

https://www.ti.com/tool/TIDA-00928

There seems to be a muxed GPMC interface implemented.
https://media.digikey.com/pdf/Data%20Sheets/Texas%20Instruments%20PDFs/TMDXICE3359_SCH.pdf

CAD symbols

CAD symbol specific to the selected device can be chosen from the device product page. Refer below:

https://www.ti.com/product/AM625SIP#cad-cae-symbols

Ordering & quality

https://www.ti.com/product/AM625SIP#order-quality

Package pad diameter and substrate pad dimension 

 ALW pkg:   ball diameter 0.3mm : substrate pad 0.25mm
The recommendation is 1:1 ratio between PCB pad and substrate pad.

Section and Document reference:

. Width/Spacing Proposal for Escapes

https://www.ti.com/lit/an/sprad13a/sprad13a.pdf

The recommendation is to use 0.25mm (10 mil) BGA landing pads to meet the requirements

Lead finish/Ball material

SnAgCuBi 

Escape Routing for PCB Design

AM62x SiP Escape Routing for PCB Design

https://www.ti.com/lit/pdf/spradd4

Note: Width/Spacing Proposal for Escapes will be updated in the next revision

Design Simulation files

https://www.ti.com/product/AM625SIP#design-tools-simulation

Simulation files provided includes IBIS, IBIS-AMI and BSDL

AM62x PDN Target impedance values:

Impedance target values for VDD_CORE 

Low freq (< 1MHz) : 22mOhm

Mid freq (1 < 20MHz) : 31 mOhm

High freq (20 < 50 MHz) : 40 mOhm

This is valid for either of the core voltage (0.75V, 0.85V) values. We do not provide target impedance values for other rails on AM62x.

For frequencies above 50 MHz the board decoupling caps do not play a critical role. SoC and Package decaps (if any) will be dominant beyond 50 MHz

Note:

We do not include Buck output inductance in PDN simulations.

For VDDS_DDR: we do not recommend using target impedance as the signoff for DDR.
Refer to theAM62x, AM62L DDR Board Design and Layout Guidelines which outlines all details of power aware SI/PI simulations
that need to be run. The eye mask checks from these power aware simulations are the signoff.

We only provide impedance targets for VDD_CORE. This information can be found under processor specific section "Example:AM62Ax" (starting on page 31) in the following document: www.ti.com/.../sprac76
As noted in the document, rails not listed are not simulated by TI due to low load transients. For more information, see the device-specific EVM layout for example implementation of these rails.
Other rails like the IOs are highly dependent on external peripherals. From the SoC perspective, if you look at the MAX current ratings for the IOs, the total current (after combining all the IOs of the same voltage) is still very low < 350mA so we don't simulate this rails/No data available.
Regarding your other questions related to PET, the supply names are not expected to match with processor (Example AM62A) pin names because the power estimates in the PET are itemized by supply groups. The power supply consolidation for these supply groups match the EVM.

Power Distribution Networks: Implementation and Analysis

Sitara Processor Power Distribution Networks: Implementation and Analysis

https://www.ti.com/lit/pdf/sprac76

Note: The decoupling capacitor numbers and type on the SK/EVM are only intended to serve as a guideline for customers. The true pass/fail criteria is the target impedance published in the PDN app note.

High Speed Board design and Signal integrity simulation 

https://www.ti.com/lit/pdf/spraar7

Technical Documents

Collaterals and application notes

https://www.ti.com/product/AM625SIP#tech-docs

Technical Support

AM625SIP Custom board design - FAQs

Previous E2E threads - Keywords AM625SIP

Starting a new thread

(2) TI E2E support forums

Useful links

Sitara family of processors FAQ master list 

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1395812/faq-custom-board-hardware-design---master-complete-list-of-faqs-for-all-sitara-processor-am62x-am64x-am243x-am335x-families

Other FAQs

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1332316/faq-am625-am623-custom-board-hardware-design---design-and-review-notes-for-reuse-of-sk-am62b-p1-schematics

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1337851/faq-am625-q1-am620-q1-custom-board-hardware-design---design-and-review-notes-for-reuse-of-sk-am62-lp-schematics

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1357533/faq-am625-am623-custom-board-hardware-design---design-and-review-notes-for-reuse-of-sk-am62b-schematics

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1347063/faq-am625sip---custom-board-hardware-design---design-and-review-notes-for-reuse-of-sk-am62-sip-schematics

https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1114327/faq-what-is-the-difference-between-rmii-slave-signaling-and-rmii-master-signaling

SOC POH
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1492996/am620-q1-the-definition-of-power-of-hour-for-automotive-grade/5736233#5736233

Notes

1. Always ensure you are using the latest version of the documentation.
2. Check the product folder regularly for the latest version.
3. On Ti.com, device product folder page, there is a "Notifications" button. Registering here enables automatic notification of device document changes.
4. If you have any queries or need clarification, use E2E to find similar queries or ask a new question

Regards,

Lavanya M R.