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SK-AM62A-LP: AM62A series MPU JTAG connection

Part Number: SK-AM62A-LP
Other Parts Discussed in Thread: TMDSEMU110-U, TMDSEMU200-U, TMDSEMU560V2STM-U

Hello,

I am designing a custom board of TI MPU, modeled AM62x.
I have been examining AM62A STARTER KIT EVM.

Here is a question I have while looking at the schematic.

In according to JTAG connection part in the schematic, bi-directional voltage translator as buffer is used to seperate XDS110 IC(placed on the EVM) and external JTAG 20 pin connector.(based on my understanding)

Is there a reason that 4 bits IC is used? (only used for TRST, TCK, TMS, TDI)
There are more pin for JTAG such as EMU0, EMU1, TDO.
I don't consider TCK buffer pins(TCK, RTCK) in this issue.

I guess I can use other 8-bit IC for all those pins, such as SN74AVC8T245RHL(this is also used for boot mode buffer in the schematic as well.)

Can I design my schematic with the pins(TRST, TCK, TMS, TDI, TDO, EMU0, EMU1) by using SN74AVC8T245RHL(8-bit)?

I wonder if it might be a problem or not.

Regards.

  • Also I have a curiosity, why the voltage translator is essentially necessary.

  • Hi HOGYUN

    In addition, Please also find Emulation and Trace Headers Technical Reference Manual (Rev. I)

    There's a chapter regarding Buffering.

    https://www.ti.com/lit/ug/spru655i/spru655i.pdf?ts=1701745659248

    Q: Where can I learn about termination and buffering?

    Let's wait for TI Champ feedback on your origiral inquery. 

    Thanks.

    Regards, 

    Jack

  • The level-translators were used to prevent a potential from being applied to device pins when the device IO power rails are turned off while the on-board debugger is still powered. Please refer to the "Steady-state max voltage at all fail-safe IO pins" parameter in the datasheet Absolute Maximum Ratings table.

    Regards,
    Paul

  • What about using one 8-bits level-translator for all external JTAG pin?

    Isn't it gonna be a problem?

    I still wonder why 3 buffers(as below) are separately applied on EVM for external JTAG pins, except clock buffer for TCK, RTCK.
    1. TRST, TCK, TMS, TDI
    2. TDO
    3. EMU0, EMU1

  • All paths through the SN74AVC8T245R device you proposed must flow in the same direction at any one time. There is no way to configure the TDO signal path to flow from the SOC to the connector while the other signals are flowing from connector to the SOC. All SOC signals must be connected to the A port and all connector signals must connect to the B port since the A port is powered by the same IO supply as the SOC signals and the B port is powered by the same IO supply as the connector signals.

    I do not know why the PCB designer used a TXS0102D to level-shift the EMU[1:0] signals. I would need to assign this thread to someone from the hardware design team if you need to know why this device was used for the EMU signals. 

    Are you designing a production PCB?  If so, why are you implementing the on-board XDS110? Most customers only place a JTAG connector on their production PCB to avoid the additional cost of the on-board XDS110 components and they connect an external debugger to the PCB when it is needed to debug an issue. We included the on-board debugger to make it easy for customers to begin development.

    Regards,
    Paul

  • First of all, there is a misunderstanding.
    I don't consider implementing on-board XDS110. I just want to put on a JTAG connector(maybe 20 pin cTI connector likely EVM) to connect external debugger.
    I have 3 types of debugger,
    - TMDSEMU110-U — XDS110 JTAG Debug Probe
    - TMDSEMU200-U — XDS200 USB Debug Probe
    - TMDSEMU560V2STM-U — XDS560Tm software v2 system trace USB debug probe

    Nextly,

    Q1. What about not using buffers to connect external debugger in the case of not applying on-board debugger?

    If it is only for preventing answered issue, it doesn't seem to be needed.
    "a potential from being applied to device pins when the device IO power rails are turned off while the on-board debugger is still powered"

    I will not use voltage translator unless this is not a problem.


    Q2. TCK and RTCK pin...
    In according to the resource explorer(linked below), TCK and RTCK(also other JTAG pins too) pins don't need clock buffer if the routing length between MPU and EMU is shorter than 6 inches.

    Could I route the signal line directly?

    dev.ti.com/.../node

    Single Device Non-buffered Configuration
    "If the EMU pins do not support core or system trace and If the routing length of all JTAG and EMU signals between the device and the emulation header are less than six inches then buffering of the JTAG signals is not necessary."


    Q3. About routing length of 6 inches...
    It is around 19~20 cm, I guess.
    What point does decide the length?
    From MPU pin to 20 pin connector for external debugger?
    Or from MPU pin to the body of external debugger?


    I will appriciate you answer all of questions.

  • The JTAG connector sources power to the debugger because it has an internal level-shifter with its SOC port powered from the target. The buffer/level-shifter components in each JTAG signal path are also operating like a switch to select between the on-board debugger or the connector. Most customers place the connector within a few inches of the processor and connect the pins directly to the SOC, with the appropriate external pull resistors.

    The signal trace length of 6 inches is not a firm requirement. Short signal traces will minimize signal distortion and signal propagation delay. The most important thing is making sure the clock signal doesn't have any non-monotonic transitions. You can always resolve timing issues by slowing down the operating frequency of TCK from the debugger.

    Regards,
    Paul