[FAQ] AM625 / AM623 / AM620-Q1 / AM625-Q1 / AM625SIP : Custom board hardware design – Processor power-sequencing requirements for power-up and power-down

Hi Board designers,
Refer below inputs for the SOC(Processor) power-sequencing requirements for power-up and power-down

1.Is there a recommended power sequence to be followed for power-up?
Follow the Power-Up Sequencing Figure and Power-Up Sequencing – Supply / Signal Assignments table of the processor specific data sheet

2.Is there a power supply ramp requirement to be followed for power-up?
Refer to Power Supply Slew Rate Requirement section and Power Supply Slew and Slew Rate figure of the processor specific data sheet

3.Is there a timing requirement to be followed between supply ramps ( supply ramp delay after the previous supply ramps)
There is not specific timing requirement to be followed between 2 supply ramps. It is recommended to ensure the previous supply ramps and is stable before start of the next supply ramp

4.Are there any other sequencing requirements that are required to be considered?
Refer to the notes below the Power-Up Sequencing – Supply / Signal Assignments table of the processor specific data sheet

5.Is there a recommended power sequence to be followed for power-down?
Follow the Power-Down Sequencing figure and Power-Down Sequencing – Supply / Signal Assignments table of the processor specific data sheet

6.Is there a power supply ramp down requirement to be followed for power-down?
We do not have any specific power supply ramp down requirements to be followed. This is use case dependent.
The power supply is recommended to be turned on after the supply voltages ramp down below 0.3V.

The important consideration is following the sequence and Power Supply Slew Rate Requirement.
The supply rails connect to different internal IP blocks that are powered as the supply ramps.
Although there is no specified time, it would be recommended to have time that allows the power supply to become stable and also allow time for the internal circuit to setup and complete the configuration.

7.In the power-down sequence, the MCU_PORz goes low after the power supplies start to ramp down. Is this expected?
It is drawn that way to represent how things actually work. Power supply supervisors will need to trigger at a voltage that is few percent lower than
the minimum valid level before it generates a reset. So the reset will occur delayed relative the beginning of the supply falling.
We expect customers to assert MCU_PORz as soon as possible to ensure the IO cells do not do something unexpected as the IO supply decays.
So they should pick a threshold for the voltage supervisor that is close to the minimum valid level without being so close that is generates
false resets. We expect customers to generate reset based on the state of all supplies, where the first one that ramps down will assert reset
as soon as possible to ensure the device is in a know state as all of the supplies continue to ramp down.

8.Could you comment on the effect of not following the power-up and power-down on SOC (Processor) performance?
The data sheet provides the recommend & tested power sequencing diagram that should be followed. We do not characterize the power-up and power-down
sequence violation as part of the validation. Violating the power down sequence could likely result in issues related to device reliability.
TI does not collect reliability data on unsupported conditions (i.e. power sequences other than recommended), therefore TI cannot say whether
the SoC will operate reliably or that it may fail at any time.

9.Are these recommendations applicable for all the Sitara family of devices
This is applicable for AM64x, AM62x, AM62Ax, AM62Px

Regards,

Sreenivasa

Hi Board designers,

Additional inputs on the supply slew rate:

The power supply slew rate is only defined for power-up. This slew rate limit is required to prevent the ESD circuits implemented on the power pins from accidently triggering. This is not a concern for power-down.

Regards,

Sreenivasa

Hi Board designers,

The power down sequence is being updated to allow the IO supply to ramp down along with the VDD_CORE supply.

Refer the power-Down sequence in the updated processor specific data sheet.

Regards,

Sreenivasa

Hi Board designers,

Additional inputs:

(+) AM6442: Power Down Sequence Restrictions - Processors forum - Processors - TI E2E support forums

The 10ms between VDD_CORE and the 3.3V IO configured in the TPS6522053 PMIC power-down sequence was tested and validated on bench using the AM64 starter kit. For any new or custom PMIC NVM configuration we recommend following the SoC requirement "VDDSHV power rails to turn off as late as the last core supply" because we have not validated a scenario where 3.3V IO stays ON for an extended time (beyond 10ms). 

The reason why TPS6522053 was configured to turn-off 3.3V IO last is because we wanted to make this PMIC configuration generic for 3.3V and 5V input supply. For example, if customers use a 5V input supply, they can replace the external power-switch with a 3.3V Buck and use the output of this Buck to supply the PMIC LDOs. Turning-OFF the 3.3V last allow customers to use this rail to supply PMIC LDOs, helping to reduce power consumption on applications using 5V input supply.  

thank you for the clarification. My use case is VSYS=5V so I understand the reason for the deviation. So I think I need to take care that the 3.3V buck discharges the 3.3V rail fast enough in order to minimize the time with 3.3V still present during power off.

Yes, it is recommended to use a DC/DC with internal active discharge. For example: TPS62A0x.  

Regards,

Sreenivasa