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TMS320C6678: TMS320C6678: How to generate multiple interrupt at GPIO using EvenCombiner

Part Number: TMS320C6678

Hi, 

We generated individual interrupts at each GPIO pin. But, We facing the multiple interrupt generation at GPIO pins into a signal. We want to use multiple interrupt generation using the Event Combiner for the GPIOs( into a signal ), How to do setups for that?

i.e. ), combine all GPIO pins (0 to 15) at a signal for interrupt.

Please give us a suggestion for the same.

Warmest regards,

Krishn Singh Chauhan

  • Krishn Singh Chauhan,

    Please have a look at page no: 2


    4213.Configuring Interrupts K1.pdf

    How to test system events and Interrupts https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1309303/faq-tms320c6678-how-to-configure-interrupts-and-test-on-keystone-i-devices---c6678

    The above example will demonstrate how to map the system events into INTC using EVENT combiner 

    I suggest you to have a look at these source codes too for the event combiner usage.

    --

    Files like "RegisterIntr_nonos.c" located at "\ti\pdk_c665x_2_0_16\packages\ti\osal\src\nonos"

    just do a search on the keyword "event combiner" in tools like source-insight etc...

    /*
     * Purpose:     Registers the interrupt for the event with the params provided
     * Description: Registers the event with the event combiner/Interrupt Vector.
     *
     * Returns:     The Hwi Handle and the return codes defined in OsalInterruptRetCode_e
     */
    OsalInterruptRetCode_e Osal_RegisterInterrupt(OsalRegisterIntrParams_t *interruptRegParams,HwiP_Handle *hwiPHandlePtr)
    {
    
        OsalInterruptRetCode_e     ret=OSAL_INT_SUCCESS;
        HwiP_Handle                hwiPHandle=NULL_PTR;
        HwiP_Params                 hwiInputParams;
    
         /* Program the corepac interrupt */
          if( (interruptRegParams->corepacConfig.isrRoutine == (void (*)(uintptr_t arg)) NULL_PTR) ||
              (interruptRegParams->corepacConfig.corepacEventNum<0)) {
              ret=OSAL_INT_ERR_INVALID_PARAMS;
          }
    
          HwiP_Params_init(&hwiInputParams);
    
          hwiInputParams.name = interruptRegParams->corepacConfig.name;
          hwiInputParams.arg  = (uintptr_t)interruptRegParams->corepacConfig.arg;
          hwiInputParams.priority = interruptRegParams->corepacConfig.priority;
          hwiInputParams.evtId = (uint32_t)interruptRegParams->corepacConfig.corepacEventNum;
    #if defined (__ARM_ARCH_7A__) || defined (__aarch64__) || defined (__TI_ARM_V7R4__)
          hwiInputParams.triggerSensitivity = interruptRegParams->corepacConfig.triggerSensitivity;
    #endif
    
    #ifdef _TMS320C6X
          /* Maps the core_event_in to the  hwi Vector core_intVecNum (4-15) for C6x and core_intNum for ARM */
    /*       For C66x
                Use Event Combiner ALWAYS for c6x. Event_combiner_event (0-3) =  core_event_in/32.
                Hook the this Event_combiner_event(0-3) to the core_intVecNum.
                if core_intVecNum is set to -1 as input, it means Let RM find a free unused vector number;
                HwiP_Create(Event_combiner_event,core_intVecNum,Event_dispatcher_plug);
    */
       if(interruptRegParams->corepacConfig.intVecNum == OSAL_REGINT_INTVEC_EVENT_COMBINER) {
          OsalArch_oneTimeInit();
          (void)EventCombinerP_dispatchPlug((uint32_t)interruptRegParams->corepacConfig.corepacEventNum,
                                      interruptRegParams->corepacConfig.isrRoutine,
                                      interruptRegParams->corepacConfig.arg,(bool)true);
    
          (void)EventCombinerP_enableEvent((uint32_t)interruptRegParams->corepacConfig.corepacEventNum);
          /* Map to a particular group */
          if(hwiInputParams.evtId > 3U) {
              /* For C66X the interrupt needs to be grouped to {0,1,2,3} to either of the four 32-bit event registers  */
            hwiInputParams.evtId= ((uint32_t)interruptRegParams->corepacConfig.corepacEventNum)/32U;
           }
           /* The dispatch function in the event combiner case is EventCombiner_dispatch */
    
           /* Find out if the event combiner is already registered, if so, dont re-register */
           hwiPHandle = EventCombinerP_getHwi(hwiInputParams.evtId);
           if(hwiPHandle==NULL_PTR) {
               /* The event hasn't been registered yet. Register it as per the defaults provided by OSAL */
               Osal_HwAttrs hwAttrs;
    
                   /* Get the default OSAL mapped ones */
               (void)Osal_getHwAttrs(&hwAttrs);
    
               /* No need to register seperately in case of baremetal , the HwiP_Create() takes care of it */
                   
              hwiPHandle =  HwiP_create(hwAttrs.ECM_intNum[hwiInputParams.evtId],interruptRegParams->corepacConfig.isrRoutine, &hwiInputParams);
           
               if(hwiPHandle==NULL_PTR) {
                  ret=OSAL_INT_ERR_EVENTCOMBINER_REG;
               } 
           } else {
              /* The Event combiner handle already exists. Now plug the ISR routine in to
                  the CSL_intcEventHandlerRecord_p */
                (void)EventCombinerP_dispatchPlug((uint32_t)interruptRegParams->corepacConfig.corepacEventNum,
                                            interruptRegParams->corepacConfig.isrRoutine,
                                            interruptRegParams->corepacConfig.arg,(bool)true);
           }
       } else {
           /* Do not use the event combiner. Use the supplied ISR routine */
           hwiPHandle =  HwiP_create(interruptRegParams->corepacConfig.intVecNum,interruptRegParams->corepacConfig.isrRoutine, &hwiInputParams);
           if(hwiPHandle ==NULL_PTR) {
              ret=OSAL_INT_ERR_HWICREATE;
           }
       }
    #else
    
    #if (defined (__ARM_ARCH_7A__) || defined (__aarch64__)) && !defined (SOC_AM437x) &&  !defined(SOC_AM335x)
        /* Initialize GIC if not done already */
        Osal_HwAttrs hwAttrs;
        (void)Osal_getHwAttrs(&hwAttrs);
        if(hwAttrs.hwAccessType==OSAL_HWACCESS_UNRESTRICTED)
        {
          /* Do GIC init only in the case of unrestricted hw access */
          OsalArch_gicInit();
        }
    #if defined(SOC_K2G) || defined (SOC_K2L) || defined (SOC_K2H) || defined (SOC_K2K) || defined (SOC_K2E)
        /* Keystone parts don't need subtract by 32 for ARM GIC ID */
    #else
        /* Subtract 32 as the IRQ handler for A15 subtracts 32, Keystone handler does not do it */
    #if !defined(__aarch64__)
        interruptRegParams->corepacConfig.intVecNum -= 32;
    #endif
    #endif
    #endif
    
       hwiPHandle =  HwiP_create(interruptRegParams->corepacConfig.intVecNum,interruptRegParams->corepacConfig.isrRoutine, &hwiInputParams);
       if(hwiPHandle ==NULL_PTR) {
           ret=OSAL_INT_ERR_HWICREATE;
       }
    #endif
    
      *hwiPHandlePtr=hwiPHandle;
      return ret ;
    }
    

    Regards

    Shankari G

  • Hi,

    OK,  

    Warmest regards,

    Krishn Singh Chauhan