OMAPL138B-EP: RVDD and PLL0_VDDA voltage drop sensitivity

Hi Patrik,

Thanks for your question.

Please expect responses in few business days.

Thanks for your patience..

Regards,

Vaibhav

Hello Patrik,

Thank you for the query.

Can you help me understand if there were no issues seen before LDO change. 

Patrik Lundgren said:

So to my questions:

- How sensitive is the OMAPL138 SoC to voltage drops on PLL0_VDDA and the RVDD pins? (it seems to me that we are still well within spec.)

- Are there any internals which might be affected by said voltage drop to cause the described behavior?  (see serial log below)

The processor ROC includes the variation in voltage plus the ripple.

Please verify if there is any change in recommendations in terms of capacitors and layout between LDOs.

Please start a E2E query with the LDO numbers as the title to get the required support from the LDO team.

Regards,

Sreenivasa

I am measureing the voltage after a capacitance of 10uF from the LDO output. I checked and we are following recommendations for the capacitances on the LDO inputs and output.

I am sorry but I am not familiar with the acronym ROC, what does it mean? Are you reffering the the allowed voltage levels for the RVDD pins? If so, we are within the interval on the input with voltage and ripple measured at 20Mhz bandwith. The range of the measured voltage + ripple is between 1.20 and 1.26V including ripple at all times. The error does seem to coincide with the sudden drop of 12mV +- ~8mV ripple.

Kallikuppa Sreenivasa said:

Can you help me understand if there were no issues seen before LDO change. 

Please provide. your thoughts.

Patrik Lundgren said:

I am sorry but I am not familiar with the acronym ROC,

Are you replacing the LDO on an existing board or is this a newly design?

Regards,

Sreenivasa 

This is a replacement on an existing board. We had no issues before the replacement.

Hello Patrik,

Thank you.

The previous LDO used was an RF LDO. 

TPS720 350 mA, Ultra-Low VIN, RF Low-Dropout Linear Regulator With Bias Pin

The current LDO is 

TPS7A11 500-mA, Low VIN, Low VOUT, Ultra-Low Dropout Regulator

I see there is difference in the input and output cap recommendations.

Can you verify all the recommended changes have been taken care.

Regards,

Sreenivasa

I am sorry but which cap recommendation are you reffering to? i have ferrite  and 3 caps.on the output BLN15HG102SN1 + 10uF + 2*100nF on the output, on the input i have 2*22uF and on the bias 22uF. I will forward your response to our hardware engineers.

Hello Patrik,

Thank you.

These are the recommended caps for the LDOs in the data sheet.

Please share the response and also let him know the previously used LDO was an RF LDO. The Hardware engineers may have the rationale on the LDO selection.

Regards,

Sreenivasa