This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

[FAQ] AM64x Common design Errors / Recommendations for Custom board hardware design – EVM / SK Schematics Design Update Note

Other Parts Discussed in Thread: SK-AM64B, TMDS64EVM

I am referring the collaterals for the below EVM / SK. 


Is there any Update to be Done on the collaterals to reuse in my custom design.

  • Hi Board designers, 

    Here are some recommended updates based on the learnings for performance improvements.

    Schematics - Design Value Updates 


    SoC IO supply rails have slew rate requirements specified.

    Refer Power Supply Slew Rate Requirement section of the data sheet.

    Add a cap 220 pF or higher on the Load switch CT (Switch slew rate control) pin.

    2. SD card power reset Load switch 

    Add a cap 220 pF or higher on the Load switch CT (Switch slew rate control) pin.

    3. eMMC supply decap

    Add decaps as required to the eMMC memory supply rails 

    4. USB VBUS divider 

    5. Provision to Bypass CMC

    6. USB power switch 

    Use power switch with OC indication. Connect the OC output of the power switch to SoC input

    7. SoC clock MCU_OSC0_XI. MCU_OSC0_XO - connecting external clock 

    DNI the R and C placed at the output of the clock buffer connected to the MCU OSC0 clock input. Placement of these components reduces the amplitude and could affect the performance

    8. SoC  MCU_OSC0_XO termination - when using external clock 

    Data sheet section reference : MCU_OSC0 LVCMOS Digital Clock Source

    Do not leave XO un connected 

    The oscillator was designed to measure the differential voltage between XI and XO, for creating a internal reference clock.  So there is no guarantee they will get the correct differential input voltage if the XO pin is allowed to float.  The datasheet clearly shows this pin needs to be connected to VSS when using an LVCMOS clock source.

    9. Ethernet PHY updates

    Take note of the following

    EPHY 1.8V supply pins when not used should not be shorted

    Note the recommended caps for the EPHY supplies

    Note the Rbias R and C values 

    Note the pulldown for the EPHY Reset