AM5716: BSDL definition of differential bidirectional signal (Boundary Scan)

Part Number: AM5716
Other Parts Discussed in Thread: AM3357

Hi,

My question also relates to the following two threads:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1006877/am5716-boundary-scan-issue-with-ddr1_dqsx-pins

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/895880/am5728-the-result-of-the-boundary-scan-test-on-am5728/3338424#3338424

We use Göpel CASCON software to boundary scan test our units.

I have still some problems to be able to correctly boundary scan test a unit that includes the AM5716AABCXEA and DDR3 SDRAM MT41K256M16TW-107XIT.
All the problems are related to the DDR1_DQS[3:0] and DDR1_DQSN[3:0] signals (differential bidirectional signals).
Those signals are defined in the BSDL file as follows (just DDR1_DQS0 and DDR1_DQSN0 shown):

ddr1_dqs0: INOUT bit;
ddr1_dqsn0: OUT bit;

"ddr1_dqsn0: AG25 , " &
"ddr1_dqsn1: AE28 , " &

"1354 (bc_1, ddr1_dqsn0, output3, X, 1355, 1, Z)," &
"1355 (bc_1, *, control, 1)," &
"1356 (bc_1, *, internal, 0)," &

"1369 (bc_1, ddr1_dqs0, output3, X, 1370, 1, Z)," &
"1370 (bc_1, *, control, 1)," &
"1371 (bc_1, ddr1_dqs0, input, X)," &

From this definition it seems that DDR1_DQS0 is bidirectional but DDR1_DQSN0 is output only.

Now our boundary scan software has a problem as this does not match with the definition of the DDR3 SDRAM pin definition. As DDR1_DQSN0 is defined as output only the software is not able to generate a test program.

If I compare those definitions with the ones for MLBP_SIG (MLBP_SIG_P and MLBP_SIG_N) which are also differential bidirectional signals I see quite some differences:

mlbp_sig_p: INOUT bit;
mlbp_sig_n: INOUT bit;

"mlbp_sig_n: AC2 , " &
"mlbp_sig_p: AC1 , " &

attribute PORT_GROUPING of AM571_top : entity is
"Differential_Voltage ( (mlbp_dat_p,mlbp_dat_n)," &
"(mlbp_clk_p,mlbp_clk_n)," &
"(mlbp_sig_p,mlbp_sig_n))" ;

"805 (bc_1, mlbp_sig_p, output3, X,806,1, Z)," &
"806 (bc_1, *, control, 1)," &
"807 (bc_1, mlbp_sig_p, input, X)," &

Is there a possibility that there is a problem with those definitions in the BSDL file?

Thanks and best regards,

Patrick

  • Hi Patrick,

    The DDR DQS differential pins should be bi-directional pins. Do you still see issues if you change the DQSN pin to INOUT in the BSDL file?

    Regards,
    Kevin

  • Hi Kevin,

    I did some test with different definitions for the DDR1_DQSN pins in the BSDL file.
    Only the following definition worked (this are the differences to the original file, shown only for DDR1_DQSN0):

    ddr1_dqsn0: INOUT bit;

    "1356 (bc_1, ddr1_dqsn0, input, X)," &


    Can you please check if this matches the internal implementation of the AM5716.

    Regards,
    Patrick

  • Hi Patrick,

    Unfortunately, I am not very familiar with BSDL and its syntax (or the history of the AM571x BSDL file), but it looks like the changes you made are probably correct. The BSDL file of similar devices, such as DRA75x, seem to have similar definition for the DQSn pin. https://www.ti.com/lit/zip/sprm667 

    I am checking to see if someone else within TI can comment; however, please let us know if this issue is resolved.

    Regards,
    Kevin

  • Hi Kevin,

    Your right, in the DRA75X those pins are defined exactly the same way.

    The problem is that those pins are often defined in different ways (e.g. AM3357). What I think is that AM5716 is not able to read pin DDR1_DQSN0 because there is probably no functional boundary scan input cell behind this pin.

    So it would be good if you can find an expert who can explain how those pins are implemented from a boundary scan perspective and what definition would match best or is correct.

    Regards,
    Patrick

  • Hi Kevin,

    Any news for this topic?

    Regards,
    Patrick