Original question:
[FAQ] TDA4VM: TDA4VM/DRA829V: routing PCIE reference clock externally
Hello,
we want to implement a Gen1 X1 PCIe interface with DRA829-Q1 SERDES0 as Root Complex and a Xilinx Ultrascale+ as End Point.
Is it possible to clock SERDES0 by Jacinto internal resources, and also to output this Clock on PCI_REFCLK0P/N to drive the Endpoint Reference Clock input?
Target is to avoid an additional external clocking device.
Could you provide a configuration example?
Regards, Peter
Hi Peter,
Is it possible to clock SERDES0 by Jacinto internal resources, and also to output this Clock on PCI_REFCLK0P/N to drive the Endpoint Reference Clock input?
Yes, and yes.
For software, the FAQ that you have found can be used as reference: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1004565/faq-tda4vm-tda4vm-dra829v-routing-pcie-reference-clock-externally. If there are any questions regarding a specific portion of this, please let us know.
For hardware, the schematic file TI "Common Processor Board Design Files (Rev. D)" files obtainable from the "Design Files" section should be referenced: https://www.ti.com/tool/J721EXSOMXEVM. Specifically the PROC079E3D(001)_SCH.pdf file in the zip file contains a section that talks about "CLOCK ROOT SELECTION" for the x1LANE PCIe Interface. Hardware modifications to the board should be made to get the device in "PCIe end point" mode to drive the PCIe connector from the internal SoC clock. I will post a screenshot of this section for convenience:
R195 (R3), R199 (R4), C92 (C1), C93 (C2) are DNI (Do Not Installs), so by default on TI EVM, the "PCIe root complex" mode where the SoC and connector both takes in an external clock is selected instead of the SoC clock. To switch to "PCIe end point" mode, we have designed the board such that these resistors can be physically desoldered, "rotated", and then soldered back on to change connection between the pads.
Regards,
Takuma
