Other Parts Discussed in Thread: SN65LVDS84A
So, I'm trying to integrate a LVDS panel via the SN65LVDS84A .
According to TI , currently the way to integrate a new panel is to make use of the TILCDC linux driver .
This driver, as far as I understand, has 2 layers The DRM part and the panel part.
This is the default set in the original beaglebone black DTS.
The plan is to drive the SN65LVDS84A from the CPU directly over DPI config and let the SN65LVDS84A convert to LVDS.
(the orignal definition to HDMI have been removed from the DTS)
At the moment I can get the DRM driver to load and create a FB0. But obviously... the panel is not working and backlight is not turning on.
The backlight controller mux did not changed from our previous known working configuration.
So one of my first questions is, am I right to use TI's TILCDC driver to drive the LVDS panel via the SN65LVDS84A ?
OR should I be using the DPI driver (the simple-panel dts config)?
What could I be missing in the DTS to get the panel to work?
Looking around .. the information online (and on TI forum) seems to go multiple ways and not being up to date.
also , we use linux-sti-staging 5.10 from the OE meta-ti layer
Thanks a lot !
&lcdc {
status = "okay";
/delete-node/ port;
};
panel {
compatible = "ti,tilcdc,panel";
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&lcdc_pins>;
backlight = <&backlight>;
// LCD_EN
enable-gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
panel-info {
ac-bias = <255>; /** AC Bias Pin Frequency **/
ac-bias-intrpt = <0>; /** AC Bias Pin Transitions per Interrupt **/
dma-burst-sz = <16>; /** DMA Burst Size **/
bpp = <16>; /** Bits per pixel **/
fdd = <0x80>; /** FIFO DMA Request Delay **/
sync-edge = <0>; /** Horizontal and Vertical Sync Edge: 0=rising 1=falling **/
sync-ctrl = <1>; /** Horizontal and Vertical Sync: Control: 0=ignore **/
raster-order = <0>; /** Raster Data Order Select: 1=Most-to-least 0=Least-to-most **/
fifo-th = <0>; /** DMA FIFO threshold **/
};
display-timings {
native-mode=<&timing0>;
timing0: 1024x728 {
hactive = <1024>;
vactive = <768>;
clock-frequency = <60000000>;
vsync-len = <2>;
hsync-len = <10>;
vfront-porch = <3>;
vback-porch = <4>;
hfront-porch = <14>;
hback-porch = <40>;
//hsync-active = <1>;
//vsync-active = <1>;
//pixelclk-active = <1>;
de-active = <0>;
};
};
};
panel {
compatible = "ti,tilcdc,panel";
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&lcdc_pins>;
backlight = <&backlight>;
// LCD_EN
enable-gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
panel-info {
ac-bias = <255>; /** AC Bias Pin Frequency **/
ac-bias-intrpt = <0>; /** AC Bias Pin Transitions per Interrupt **/
dma-burst-sz = <16>; /** DMA Burst Size **/
bpp = <16>; /** Bits per pixel **/
fdd = <0x80>; /** FIFO DMA Request Delay **/
sync-edge = <0>; /** Horizontal and Vertical Sync Edge: 0=rising 1=falling **/
sync-ctrl = <1>; /** Horizontal and Vertical Sync: Control: 0=ignore **/
raster-order = <0>; /** Raster Data Order Select: 1=Most-to-least 0=Least-to-most **/
fifo-th = <0>; /** DMA FIFO threshold **/
};
display-timings {
native-mode=<&timing0>;
timing0: 1024x728 {
hactive = <1024>;
vactive = <768>;
clock-frequency = <60000000>;
vsync-len = <2>;
hsync-len = <10>;
vfront-porch = <3>;
vback-porch = <4>;
hfront-porch = <14>;
hback-porch = <40>;
de-active = <1>;
};
};
};
lcdc_pins: pinmux_lcdc_pins {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) /* LCD_DATA0 */
AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) /* LCD_DATA1 */
AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) /* LCD_DATA2 */
AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) /* LCD_DATA3 */
AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) /* LCD_DATA4 */
AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) /* LCD_DATA5 */
AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) /* LCD_DATA6 */
AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) /* LCD_DATA7 */
AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) /* LCD_DATA8 */
AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) /* LCD_DATA9 */
AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) /* LCD_DATA10 */
AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) /* LCD_DATA11 */
AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) /* LCD_DATA12 */
AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) /* LCD_DATA13 */
AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) /* LCD_DATA14 */
AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) /* LCD_DATA15 */
AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) /* LCD_DE */
AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) /* LCD_CLK */
/* bbek4l mods */
AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE7) /* LCD_VSYNC */
AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE7) /* LCD_HSYNC */
AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE7) /* LCD_EN for SN65LVDS84AQDGG */
AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE7) /* LCD_POWER_EN both the LCD backlight and SN65LVDS84AQDGG */
>;
};