DRA829J-Q1: OSPI Timing Requirements

Part Number: DRA829J-Q1
Other Parts Discussed in Thread: DRA829J,

The data sheet SPRSP79B from december 2023 shows a reworked OSPI Timing chapter compared to SPRSP35J (August 2021), especially shorter setup/hold times for SDR mode are given.

Is the timing chapter of SPRSP79B also applicable for DRA829J devices or is there a difference in die/bonding/... between DRA829J and TDA4VP which lead to a different timing?

Regards, Peter

  • Hello TI-Team,

    according to DRA829J datasheet, the max. achievable performance, when connecting a QSPI flash, is limited to a clock of ~55MHz (due to the specified setup/hold times), compared to a max. of >130MHz -> very low performance, which does not comply with our expectation.

    Therefore the question above is of high interest, if we can consider shorter setup/hold times in a future update of the DRA829J-Q1 datasheet.

    Could you please provide a status on this topic?

    Thank you!

  • Data Training mode should be used to support higher frequencies of operation (ex. 133MHz, and 166MHz).

  • Hi B.C.,

    does it mean that for the lower frequencies, e.g. 100MHz, data training is not required?


  • Without data training, the options are to run in Tap Mode (50MHz SDR) or PHY Mode without Data Training. I assume that the 55MHz number that Cornelius provided above was based on performing a timing analysis with an external flash using the PHY Mode without Data Training timings? If so, then that is likely the fastest you can run without data training.

    Any reason that you don't want to use data training to run at higher speeds?