TDA4VM: How to add the number of CAN channels

Part Number: TDA4VM

Hi Team,

1. The ti-processor-sdk-rtos-j721e-evm-09_00_00_02 supports only four CAN channels, namely MCU_MCAN0 and MCU_MCAN1 in the MCU domain and MCAN0 and MCAN1 in the main domain.
2. Due to development requirements, we need to enable MCAN2, MCAN3 and MCAN4 in the main domain. May I ask how to open these three can channels.

Regards,

Yousheng Liu

  • Hello,

    All CAN channels are enabled to use , are you saying in example we didn't use so you are thinking channels are disabled?

    Regards

    Tarun MUkesh

  • It's possible that I have expressed it incorrectly.

    MCAN2, MCAN3, and MCAN4 have already been enabled, but I noticed that these 3 CAN channels are still forbidden. Where can I activate them?

    Regards,

    Yousheng Liu

  • Hi

    It's possible that I have expressed it incorrectly before.

    MCAN2, MCAN3, and MCAN4 have already been enabled in rtos, but I noticed that these 3 CAN channels are still forbidden. Where can I activate them?

    CanApp_Startup.c as follows

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    /**
     *  \file     CanApp_Startup.c
     *
     *  \brief    This file contains the pinmux, interrupt and clock configuration.
     */
    /* ========================================================================== */
    /*                             Include Files                                  */
    /* ========================================================================== */
    #include "CanApp_Startup.h"
    #include "can_profile.h"
    #include <ti/csl/csl_types.h>
    
    
    /* ========================================================================== */
    /*                            Global Variables                                */
    /* ========================================================================== */
    uint32                      CanApp_IntNumbers[CAN_MAX_CONTROLLER];
    /**< Store the interrupt numbers for all enabled CAN instances */
    uint32                      CanApp_InstanceSrcId[CAN_MAX_CONTROLLER];
    /**< Store the interrupt source id for all enabled CAN instances */
    CanApp_IsrType              CanApp_Isr[CAN_MAX_CONTROLLER];
    /**< Associated ISR */
    uint32                      CanApp_RoutIntNumbers[CAN_MAX_CONTROLLER];
    /**< Store the output interrupt number routed */
    extern Can_PduType          CanApp_Pdu, CanApp_Pdu1;
    /**< Variable used for copying protocol data unit */
    extern uint8                CanApp_InputData[64U];
    /**< Variables which contains Can PDU data used in Can transmission */
    extern const Can_PduType    *CanApp_PduInfo;
    /**< Variable which contains Can PDU data passed during Transmission */
    /* ========================================================================== */
    /*                          Function Definitions                              */
    /* ========================================================================== */
    /** \brief Start up sequence : Program the interrupt muxes / priorities */
    void CanApp_Startup(void)
    {
        /* Build Interrupt list for the enabled Can Instances */
        CanApp_BuildIntList();
        Intc_Init();    /* Interrupt handler initialized, here as other functions
                         * can use API's to clear pending interrupts if any
                         */
    
        /* Interrupt configuration for the enabled Can Instances */
        CanApp_InterruptConfig();
    
        /* Initialize counters, that would be required for profiling operations */
        AppUtils_ProfileInit(0);
    
        /* Initialize memory sections, which is used to check memory corruption */
    	AppUtils_CanSectionInit();
    
    }
    
    void CanApp_BuildIntList(void)
    {
        uint32 idx, flag, intNum;
        const Can_ConfigType *Can_ConfigPtr;
        CanApp_IsrType pIsrHandler = NULL;
        uint32 canMaxControllerCnt = 0U;
        uint32 canDevId, routIntNum = 0U;//20230419
    
        /*
         * 1. Determine the number of Can Instances used
         * 2. Build valid Can Instances list
         * 3. Build isr and interrupt number for enabled Can Instances only
         */
        /* Do Can Init */
    #if (STD_ON == CAN_VARIANT_PRE_COMPILE)
        Can_ConfigPtr = &CAN_INIT_CONFIG_PC;
        Can_Init((const Can_ConfigType *) NULL_PTR);
    #if (CAN_INITIAL_PRINT_DISABLE_BEFORE_CAN_RESPONSE == STD_OFF)
        /*AppUtils_Printf(MSG_NORMAL, MSG_APP_NAME
                        "Variant - Pre Compile being used !!!\n");*/
    #endif
    #else
        Can_ConfigPtr = &CanConfigSet;
        Can_Init(Can_ConfigPtr);
    #if (CAN_INITIAL_PRINT_DISABLE_BEFORE_CAN_RESPONSE == STD_OFF)
        AppUtils_Printf(MSG_NORMAL, MSG_APP_NAME
                        "Variant - Post Build being used !!!\n");
    #endif
    #endif
    
        /* Enable SCI Client */
        Sciclient_init(NULL_PTR);
        canMaxControllerCnt = Can_ConfigPtr->CanMaxControllerCount;
        for (idx = 0U; idx < canMaxControllerCnt; idx++)
        {
            CanApp_IntNumbers[idx] = 0U;
            CanApp_InstanceSrcId[idx] = 0U;
            CanApp_RoutIntNumbers[idx] = 0U;        
        }
        
        for (idx = 0U; idx < canMaxControllerCnt; idx++)
        {
            flag = 0U;
            if (CAN_CONTROLLER_INSTANCE_MCU_MCAN0 ==
                CanConfigSet_CanController_List_PC[idx]->CanControllerInst)
            {
                intNum = APP_MCU_MCAN_0_INT0;
                pIsrHandler = Can_0_Int0ISR;
                canDevId = TISCI_DEV_MCU_MCAN0;//20230419
                flag = 1U;
            }
            if (CAN_CONTROLLER_INSTANCE_MCU_MCAN1 ==
                CanConfigSet_CanController_List_PC[idx]->CanControllerInst)
            {
                intNum = APP_MCU_MCAN_1_INT0;
                pIsrHandler = Can_1_Int0ISR;
                canDevId = TISCI_DEV_MCU_MCAN1;//20230419
                flag = 1U;           
            }
            //20230419
            if (CAN_CONTROLLER_INSTANCE_MCAN0 ==
                CanConfigSet_CanController_List_PC[idx]->CanControllerInst)
            {
                intNum = APP_MCAN_0_INT0;//16U
                pIsrHandler = Can_2_Int0ISR;
                routIntNum = INTRTR_CFG_MAIN_DOMAIN_MCAN_0_OUT_INT_NO +
                    INTRTR_CFG_START_LEVEL_INT_NUMBER;//28+160
                canDevId = TISCI_DEV_MCAN0;
                flag = 1U;
            } 
            //20230505 Add Main_MCAN1
            if (CAN_CONTROLLER_INSTANCE_MCAN1 ==
                CanConfigSet_CanController_List_PC[idx]->CanControllerInst)
            {
                intNum = APP_MCAN_1_INT0;//19U
                pIsrHandler = Can_3_Int0ISR;
                routIntNum = INTRTR_CFG_MAIN_DOMAIN_MCAN_1_OUT_INT_NO +
                    INTRTR_CFG_START_LEVEL_INT_NUMBER;//29+160
                canDevId = TISCI_DEV_MCAN1;
                flag = 1U;
            }
            //20230508 Add Main_MCAN2
            if (CAN_CONTROLLER_INSTANCE_MCAN2 ==
                CanConfigSet_CanController_List_PC[idx]->CanControllerInst)
            {
                intNum = APP_MCAN_2_INT0;//22U
                pIsrHandler = Can_4_Int0ISR;
                routIntNum = INTRTR_CFG_MAIN_DOMAIN_MCAN_2_OUT_INT_NO +
                    INTRTR_CFG_START_LEVEL_INT_NUMBER;//30+160
                canDevId = TISCI_DEV_MCAN2;
                flag = 1U;
            }
            //20230508 Add Main_MCAN3
            if (CAN_CONTROLLER_INSTANCE_MCAN3 ==
                CanConfigSet_CanController_List_PC[idx]->CanControllerInst)
            {
                intNum = APP_MCAN_3_INT0;//25U
                pIsrHandler = Can_5_Int0ISR;
                routIntNum = INTRTR_CFG_MAIN_DOMAIN_MCAN_3_OUT_INT_NO +
                    INTRTR_CFG_START_LEVEL_INT_NUMBER;//31+160
                canDevId = TISCI_DEV_MCAN3;
                flag = 1U;
            }  
            //20230508 Add Main_MCAN4
            if (CAN_CONTROLLER_INSTANCE_MCAN4 ==
                CanConfigSet_CanController_List_PC[idx]->CanControllerInst)
            {
                intNum = APP_MCAN_4_INT0;//278U
                pIsrHandler = Can_6_Int0ISR;
                routIntNum = INTRTR_CFG_MAIN_DOMAIN_MCAN_4_OUT_INT_NO +
                    INTRTR_CFG_START_LEVEL_INT_NUMBER;//32+160
                canDevId = TISCI_DEV_MCAN4;
                flag = 1U;
            }                                      
            if (0U != flag)
            {
                CanApp_IntNumbers[idx] = intNum;
                CanApp_Isr[idx] = pIsrHandler;
                CanApp_InstanceSrcId[idx] = canDevId;//20230419
                CanApp_RoutIntNumbers[idx] = routIntNum;//20230419            
                flag = 0U;
            }
        }
    
        return;
    }
    
    void CanApp_PlatformInit()
    {
        uint32 regVal = 0U;
        /* Unlock lock key registers for Partition 7: IO PAD
           configuration registers in MAIN_CTRL_MMR */
        /* write Partition 7 Lock Key 0 Register */
        CSL_REG32_WR(CSL_WKUP_CTRL_MMR0_CFG0_BASE + 0x1D008, 0x68EF3490);
        /* write Partition 7 Lock Key 1 Register */
        CSL_REG32_WR(CSL_WKUP_CTRL_MMR0_CFG0_BASE + 0x1D00C, 0xD172BC5A);
        /* Check for unlock */
        regVal = CSL_REG32_RD(CSL_WKUP_CTRL_MMR0_CFG0_BASE + 0x1D008);
        while ((regVal & 0x1) != 0x1U)
        {
            regVal = CSL_REG32_RD(CSL_WKUP_CTRL_MMR0_CFG0_BASE + 0x1D008);
        }
    
        /* Unlock lock key registers for Partition 7: IO PAD
           configuration registers in MAIN_CTRL_MMR */
        /* write Partition 7 Lock Key 0 Register */
        CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + 0x1D008, 0x68EF3490);
        /* write Partition 7 Lock Key 1 Register */
        CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + 0x1D00C, 0xD172BC5A);
        /* Check for unlock */
        regVal = CSL_REG32_RD(CSL_CTRL_MMR0_CFG0_BASE + 0x1D008);
        while ((regVal & 0x1) != 0x1U)
        {
            regVal = CSL_REG32_RD(CSL_CTRL_MMR0_CFG0_BASE + 0x1D008);
        }
    
        /* Unlocking done */
        /* Below code will be replaced by Port module in further releases */
        /* MCU MCAN 0 Tx PAD configuration */
        regVal = 0x60000U;
        CSL_REG32_WR(CSL_WKUP_CTRL_MMR0_CFG0_BASE + 0x1C0A8U, regVal);
        /* MCU MCAN 0 Rx PAD configuration */
        regVal = 0x60000U;
        CSL_REG32_WR(CSL_WKUP_CTRL_MMR0_CFG0_BASE + 0x1C0ACU, regVal);
        /* MCU MCAN 1 Tx PAD configuration */
        regVal = 0x60000U;
        CSL_REG32_WR(CSL_WKUP_CTRL_MMR0_CFG0_BASE + 0x1C0C0U, regVal);
        /* MCU MCAN 1 Rx PAD configuration */
        regVal = 0x60000U;
        CSL_REG32_WR(CSL_WKUP_CTRL_MMR0_CFG0_BASE + 0x1C0C4U, regVal);
    
        /* MAIN MCAN 0 Tx PAD configuration */
        regVal = 0x60000U;
        CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + 0x1C20CU, regVal);
        /* MAIN MCAN 0 Rx PAD configuration */
        regVal = 0x60000U;
        CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + 0x1C208U, regVal); 
    
        /* MAIN MCAN 1 Tx PAD configuration */
        regVal = 0x60000U;
        CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + 0x1C214U, regVal);
        /* MAIN MCAN 1 Rx PAD configuration */
        regVal = 0x60000U;
        CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + 0x1C210U, regVal); 
    
        /* MAIN MCAN 2 Tx PAD configuration */
        regVal = 0x60003U;
        CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + 0x1C21CU, regVal);
        /* MAIN MCAN 2 Rx PAD configuration */
        regVal = 0x60003U;
        CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + 0x1C218U, regVal);
    
        /* MAIN MCAN 3 Tx PAD configuration */
        regVal = 0x60001U;
        CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + 0x1C204U, regVal);
        /* MAIN MCAN 3 Rx PAD configuration */
        regVal = 0x60001U;
        CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + 0x1C200U, regVal);    
    
        /* MAIN MCAN 4 Tx PAD configuration */
        regVal = 0x60006U;
        CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + 0x1C020U, regVal);
        /* MAIN MCAN 4 Rx PAD configuration */
        regVal = 0x60006U;
        CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + 0x1C024U, regVal);
        /* Take MCAN transceivers out of STB mode i.e NORMAL Mode */
        CanApp_EnableTransceivers();
    }
    
    void CanApp_EnableTransceivers(void)
    {
        uint32 regVal = 0U;
        Dio_LevelType dioPinLevel[2U];
    
        /* Take MCAN transceiver out of STB mode for MCU MCAN0 */
        /* Below code will be replaced by Port module in further releases */
        /* Pin mux configuration of Dio Pin 15(MCU_MCAN0_EN J27 WKUP_GPIO0_15) */
        regVal = 0x08050007U;
        CSL_REG32_WR(CSL_WKUP_CTRL_MMR0_CFG0_BASE + CSL_WKUP_CTRL_MMR_CFG0_PADCONFIG59, regVal);
        /* Set Pin direction to output */
        regVal = CSL_REG32_RD(CSL_WKUP_GPIO0_BASE + 0x10U);                                                        
    
        regVal &= (~(1U << 0x0FU));
        CSL_REG32_WR(CSL_WKUP_GPIO0_BASE + 0x10U, regVal);
        /* Drive Pin to High */
        Dio_WriteChannel(15U, STD_HIGH);
         /* Read Pin level */
        dioPinLevel[1U] = Dio_ReadChannel(15U);
        /*Read back the pin levels to ensure transceiver is enabled*/
        if (STD_HIGH != dioPinLevel[1U])
        {
            AppUtils_Printf(MSG_NORMAL, MSG_APP_NAME
            " Error in Enabling CAN Transceiver MCU MCAN0!!!\n");
        }
        else
        {
            /* Pin mux configuration of Dio Pin 51(MCU_CAN0_STBZ F23 WKUP_GPIO0_51) */
            regVal = 0x08050007U;
            CSL_REG32_WR(CSL_WKUP_CTRL_MMR0_CFG0_BASE +
                CSL_WKUP_CTRL_MMR_CFG0_PADCONFIG35, regVal);            
            /* Set Pin direction to output */
            regVal = CSL_REG32_RD(CSL_WKUP_GPIO0_BASE + 0x38U);
            regVal &= (~(1U << 0x13U));
            CSL_REG32_WR(CSL_WKUP_GPIO0_BASE + 0x38U, regVal);
            /* Drive Pin to High */
            Dio_WriteChannel(51U, STD_HIGH);
             /* Read Pin level */
            dioPinLevel[1U] = Dio_ReadChannel(51U);
            /*Read back the pin levels to ensure transceiver is enabled*/
            if (STD_HIGH != dioPinLevel[1U])
            {
                AppUtils_Printf(MSG_NORMAL, MSG_APP_NAME
                " Error in Enabling CAN Transceiver MCU MCAN0!!!\n");
            }
            else
            {
                /*AppUtils_Printf(MSG_NORMAL, MSG_APP_NAME
                " Successfully Enabled CAN Transceiver MCU MCAN0!!!\n");*/
            }
        }
    
        return;
    }
    
    void CanApp_InterruptConfig(void)
    {
        uint32 idx;
        OsalRegisterIntrParams_t    intrPrms;
        OsalInterruptRetCode_e      osalRetVal;
        HwiP_Handle hwiHandle;
        struct tisci_msg_rm_irq_set_req     rmIrqReq;//20230504
        struct tisci_msg_rm_irq_set_resp    rmIrqResp;//20230504
        Int32 retVal;//20230504    
        const Can_ConfigType *Can_ConfigPtr;
        uint32 AddressOffset,regVal = 0;
    #if (STD_ON == CAN_VARIANT_PRE_COMPILE)
        Can_ConfigPtr = &CAN_INIT_CONFIG_PC;
    #else
        Can_ConfigPtr = &CanConfigSet;
    #endif
        /*set MAIN2MCU_LVL_INTRTR0_MUXCNTL_n n= 0 ~ 63*/
        regVal |= (1U << 16U);//INT_ENABLE
        regVal |= APP_MCAN_4_INT0;//MAIN2MCU_LVL_INTRTR0_IN_278
        AddressOffset = (4 + 32*4);//
        CSL_REG32_WR(CSL_MAIN2MCU_LVL_INTRTR0_CFG_BASE + AddressOffset, regVal);//Page13473 MAIN2MCU_LVL_INTRTR0_MUXCNTL_n Register
        AddressOffset = 0;
    
        for (idx = 0U; idx < Can_ConfigPtr->CanMaxControllerCount; idx++)
        {
            /* If the CAN instance is not in MCU domain, the interrupt router will
                have to be configured */
            /* Set the destination interrupt */
            if ((CAN_CONTROLLER_INSTANCE_MCU_MCAN0 !=
                CanConfigSet_CanController_List_PC[idx]->CanControllerInst) &&
               (CAN_CONTROLLER_INSTANCE_MCU_MCAN1 !=
                CanConfigSet_CanController_List_PC[idx]->CanControllerInst))
            {
                CanApp_IntNumbers[idx] = CanApp_RoutIntNumbers[idx];          
                rmIrqReq.valid_params           = TISCI_MSG_VALUE_RM_DST_ID_VALID;
                rmIrqReq.valid_params          |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
                rmIrqReq.src_id                 = CanApp_InstanceSrcId[idx];
                rmIrqReq.global_event           = 0U;
                /* Src Index 0 - mcanss_ext_ts_rollover_lvl_int,
                   Src Index 1 - mcanss_mcan_lvl_int Line 0,
                   Src Index 2 - mcanss_mcan_lvl_int Line 1 */
                rmIrqReq.src_index              = 1U;
                rmIrqReq.dst_id                 = TISCI_DEV_MCU_R5FSS0_CORE0;
                rmIrqReq.dst_host_irq           = CanApp_RoutIntNumbers[idx];
                rmIrqReq.ia_id                  = 0U;
                rmIrqReq.vint                   = 0U;
                rmIrqReq.vint_status_bit_index  = 0U;
                rmIrqReq.secondary_host         = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;
                retVal = Sciclient_rmIrqSet(
                             &rmIrqReq, &rmIrqResp, APP_SCICLIENT_TIMEOUT);
                if(CSL_PASS != retVal)
                {
                    AppUtils_Printf(MSG_NORMAL,
                    "CAN_APP: Error in SciClient Interrupt Params Configuration %d !!!\n",idx);
                }
            }
    
            Osal_RegisterInterrupt_initParams(&intrPrms);
            intrPrms.corepacConfig.arg          = (uintptr_t)CanApp_Isr[idx];
            intrPrms.corepacConfig.isrRoutine   = &CanApp_CanXIsr;
            intrPrms.corepacConfig.priority     = 1U;
            intrPrms.corepacConfig.corepacEventNum = 0U; /* NOT USED ? */
            intrPrms.corepacConfig.intVecNum        = CanApp_IntNumbers[idx];
            
            osalRetVal = Osal_RegisterInterrupt(&intrPrms, &hwiHandle);
    
            if(OSAL_INT_SUCCESS != osalRetVal)
            {
                AppUtils_Printf(MSG_NORMAL,
                                "CAN_APP: Error %d !!!\n",idx);
                break;
            }
        }
        /*
        for (idx = 0U; idx < 64; idx++)
        {
            AddressOffset = 4 + idx*4;
            regVal = CSL_REG32_RD(CSL_MAIN2MCU_LVL_INTRTR0_CFG_BASE + AddressOffset);
            //MAIN2MCU_LVL_INTRTR0 0~27 and 50~62 have no value
            AppUtils_Printf(MSG_NORMAL,"CAN_APP_RouteNo MAIN2MCU_LVL_INTRTR0: %d, %0x\n",idx,regVal);
        }
        */
        return;
    }
    
    /** \brief None, SBL/GEL powers up the timers and clock sources */
    void CanApp_PowerAndClkSrc(void)
    {
        /* Mcu module, when included will replace this operation */
        return;
    }
    
    void CanApp_SetupCanFrame(uint32 ctlr_cnt, uint8 *hth, uint32 *mask)
    {
    #if (CAN_TX_ONLY_MODE == STD_ON)
            if (CAN_CONTROLLER_INSTANCE_MCU_MCAN0 ==
                CanConfigSet_CanController_List_PC[ctlr_cnt]->CanControllerInst)
            {
                /* CAN Protocol Data Unit */
                CanApp_PduInfo = &CanApp_Pdu;
                /* Hardware Transmit Handle assigned to MCAN0 */
                *hth     = CAN_HTRH_0;
                /* mask is need for checking id of received message with
                 * sent message as 30th bit the of sent message will be set
                 * for CAN FD frame */
    #if (CAN_LOOPBACK_ENABLE == STD_ON) || (CAN_EXT_LOOPBACK == STD_ON)
                *mask    = 0xC0000000U;
    #endif
            }
    
            if (CAN_CONTROLLER_INSTANCE_MCU_MCAN1 ==
                CanConfigSet_CanController_List_PC[ctlr_cnt]->CanControllerInst)
            {
                /* CAN Protocol Data Unit */
                CanApp_PduInfo = &CanApp_Pdu1;
                /* Hardware Transmit Handle assigned to MCAN1 */
                *hth     = CAN_HTRH_2;
                /* mask is need for checking id of received message with
                 * sent message as 30th bit the of sent message will be set
                 * for CAN FD frame */
    #if (CAN_LOOPBACK_ENABLE == STD_ON) || (CAN_EXT_LOOPBACK == STD_ON)
                *mask = 0xC0000000U;
    #endif
            }
    #endif
    }
    
    #if (CAN_EXT_LOOPBACK == STD_ON)
    Std_ReturnType CanApp_SetupControllersExternalLoopback(uint32 CanControllerTransition)
    { 
        Std_ReturnType      statusTxCan, statusRxCan;
        Std_ReturnType      status = E_OK;
    
        if (CanControllerTransition == CAN_CS_STARTED)
        {
            statusTxCan = Can_SetControllerMode(
            CanConfigSet_CanController_List_PC[APP_MCU_MCAN0_IDX]->ControllerId, CAN_CS_STARTED);
            statusRxCan = Can_SetControllerMode(
            CanConfigSet_CanController_List_PC[APP_MCU_MCAN1_IDX]->ControllerId, CAN_CS_STARTED);
            if ((statusTxCan != E_OK) && (statusRxCan != E_OK))
            {
                status = E_NOT_OK;
            }
        }
    
        if (CanControllerTransition == CAN_CS_STOPPED)
        {
            statusTxCan = Can_SetControllerMode(
            CanConfigSet_CanController_List_PC[APP_MCU_MCAN0_IDX]->ControllerId, CAN_CS_STOPPED);
            statusRxCan = Can_SetControllerMode(
            CanConfigSet_CanController_List_PC[APP_MCU_MCAN1_IDX]->ControllerId, CAN_CS_STOPPED);
            if ((statusTxCan != E_OK) && (statusRxCan != E_OK))
            {
                status = E_NOT_OK;
            }
        }
    
        return status;
    }
    
    void CanApp_SetupCanFrameExternalLoopback(uint8 *hth, uint32 *mask)
    {
        /* Setup Can frame, reception happens on MCAN9 */
        /* CAN Protocol Data Unit */
        CanApp_PduInfo = &CanApp_Pdu1;
        /* Hardware Transmit Handle assigned to MCAN4 */
        *hth     = CAN_HTRH_0;
        /* mask is need for checking id of received message with
         * sent message as 30th bit the of sent message will be set
         * for CAN FD frame */
        *mask    = 0xC0000000U;
    }
    #endif
    

    Regards,

    Yousheng Liu

  • Hello,

    Let me check your application. 

    Few instances are on GESI board you need to use I2C to write into those.

    Regards

    Tarun Mukesh

  • Hello,

    1.We are utilizing MCAN0, MCAN1, MCAN2, MCAN3, MCAN4 and routing the interrupt to MCU_R5F1_0. The interrupt route numbers are 160+28, 160+29, 160+30, 160+31, 160+32 respectively.

    2.MCAN0 and MCAN1 can send and receive messages normally

    3.MCAN2 and MCAN3 can route successfully but cannot send or receive messages.

    4.MCAN4 routing failed,  and the return value of calling Sciclient_rmIrqSet is always CSL_FAIL.

    Regards,

    Yousheng Liu

  • Hello,

    MCAN2,MCAN3,MCAN4 all are not pinned out on TI EVM.Are you testing it with any custom board ?

    Please check with internal loop back test to ensure the problem is not in CAN transceiver configuration.

    Regards

    Tarun Mukesh 

  • Hi,

    1.We use boards of our own design for development.

    2.Check that the TXD and RXD pin configurations of the can transceiver are correct.

    3.CAN transceivers TXD and RXD have been maintained around 2.5v by multimeter measurement.

    Regards,

    Yousheng Liu

  • Hello,

    I suspect pin mux/transceiver configuration is not matching your custom board.Please run internal loop back test on MCAN2/3/4 so that we can further debug this based on result.

    We are utilizing MCAN0, MCAN1, MCAN2, MCAN3, MCAN4 and routing the interrupt to MCU_R5F1_0. The interrupt route numbers are 160+28, 160+29, 160+30, 160+31, 160+32 respectively.

    Interrupt routing numbers are correct.

    Regards

    Tarun Mukesh