TDA4AP-Q1: How to enable MSMC L3 cache and test if working

Thomas Willetal

Prodigy 121 points

Part Number: TDA4AP-Q1

Hi,

we want to configure some part of the MSMC as L3 cache.

Some information to the environment:

Board: J784s4 custom board
PDK: 9.01.00.22
Linux
SPL Boot

At the ti-dm firmware running at mcu1_0 the "sciclient_defaultBoardcfg.c" is adjusted that 2MB (.msmc_cache_size = 0x8) are activated.

diff --git a/krc5_mcu1_0/ti-pdk/pdk_j784s4_09_01_00_22/packages/ti/drv/sciclient/soc/V6/sciclient_defaultBoardcfg.c b/krc5_mcu1_0/ti-pdk/pdk_j784s4_09_01_00_22/packages/ti/drv/sciclient/soc/V6/sciclient_defaultBoardcfg.c
index b07a55e..b1bb18c 100644
--- a/krc5_mcu1_0/ti-pdk/pdk_j784s4_09_01_00_22/packages/ti/drv/sciclient/soc/V6/sciclient_defaultBoardcfg.c
+++ b/krc5_mcu1_0/ti-pdk/pdk_j784s4_09_01_00_22/packages/ti/drv/sciclient/soc/V6/sciclient_defaultBoardcfg.c
@@ -110,7 +110,7 @@ __attribute__(( aligned(128), section(".boardcfg_data") )) =
          * be given in steps of 4, which makes the size of cache to be
          * configured in steps on X/8 MB.
          */
-        .msmc_cache_size = 0x00,
+        .msmc_cache_size = 0x8,
     },
 
     /* tisci_boardcfg_dbg_cfg */

Is there a possibility to detect if this new activated L3-cache is recognized by the Linux.
I have tried for example "lshw" to show the available cache, but it looks like the new L3 cache is not available.
Is there another way to check if this MSMC L3 cache is being used?

# lshw -C memory                                              
  *-cache                   
       description: L1 Cache
       physical id: 0
       size: 32KiB
  *-cache
       description: L1 Cache
       physical id: 0
       size: 32KiB
  *-cache
       description: L1 Cache
       physical id: 0
       size: 32KiB
  *-cache
       description: L1 Cache
       physical id: 0
       size: 32KiB
  *-cache
       description: L1 Cache
       physical id: 0
       size: 32KiB
  *-cache
       description: L1 Cache
       physical id: 0
       size: 32KiB
  *-cache
       description: L1 Cache
       physical id: 0
       size: 32KiB
  *-cache
       description: L1 Cache
       physical id: 0
       size: 32KiB
  *-memory
       description: System memory
       physical id: a
       size: 3649MiB

Thanks Regards

Thomas

11 months ago

0 Fabiana Jaimes 11 months ago

TI__Mastermind 18820 points

Hi Thomas,

The assigned engineer is currently out of office this week. Please expect a delay in response.

Thank you,

Fabiana

0 Keerthy J 11 months ago in reply to Fabiana Jaimes

TI__Guru**** 156610 points

Hi Thomas,

https://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-j784s4/09_02_00_05/exports/docs/linux/How_to_Guides/FAQ/How_to_Configure_MSMC_memory.html

You can do similar configurations in the SPL U-Boot flow as shown in the above link.

No direct commands to check your size of l3 cache. Crude way would be to access the region from bottom towards the top.

There is an MMR which can be read but it would also need some lookup to check the size.

Best Regards,

Keerthy

0 Thomas Willetal 11 months ago in reply to Keerthy J

Prodigy 121 points

Hi Keerthy,

Thank you very much for the answer, but I still have some questions.

1. Question about parameterization via uboot-spl-r5

During the uboot build process the binary "combined-tifs-cfg" is created and is containing some settings. One of these is the board configuration with the required "msmc_cache_size" parameter.

ImagePos    Offset      Size  Name
00000000  00000000  000011ac  combined-tifs-cfg
00000000   00000000  000011ac  ti-board-config
<none>      00000000  0000001d  board-cfg
<none>      0000001d  0000015d  sec-cfg
<none>      0000017a  00000002  pm-cfg
<none>      0000017c  0000100e  rm-cfg

The "combined-tifs-cfg_gp.bin" is loaded to the address load-sysfw-data=0x66800.

Is there any change to verify if these board configuration are really written?
I have tried to read the memory area 0x66800 with the assistance of a JTAG debugger.
But only zero's are visible, maybe the memory area is locked?

2. MSMC L3-cache and cyclictest

Our system is a preempt rt kernel and stressed with stress-ng. If the stress-ng parameters
(--cache-level 3 --cache 4 --cache-no-affinity) are set, the latency increases drastically. The result of the
cyclic test is always the same regardless if the L3-cache is activated or not.

Do we something wrong or maybe the MSMC L3-cache is not activated?

Kind Regards
Thomas

+1 Keerthy J 11 months ago in reply to Thomas Willetal

TI__Guru**** 156610 points

Thomas Willetal said:
there any change to verify if these board configuration are really written

From U-Boot you can use:

md 0x70000000

md 0x70100000

And so on till 0x70700000

In steps of 1MB. If L3 cache is enabled then from the that size will not be accessible towards the end.

Thomas Willetal said:
Do we something wrong or maybe the MSMC L3-cache is not activated?

Try the steps suggested for 1 and check.

Best Regards,

Keerthy

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TDA4AP-Q1: How to enable MSMC L3 cache and test if working