AM6442: Serdes input clock (SERDES0_REFCLK)

Expert 2961 points

Other Parts Discussed in Thread: AM6442

May I have question about external serdes refclk?

My customer is using AM6442 and serdes use for PCIe.

I think EVM is using HCSL 100MHz clock.

Can only input HCSL level clock generator?

Q2 :

In TRM, looks Serdes can use internal clock.

If use this internal clock, Is external clock input not need?

Q3 :

I think Serdes supporting 19.2, 20, 24, 25, 26, 27, 100MHz clock frequency.

Is this mean Refclk input frequency?

Or Refclk input is 100MHz or 125MHz only, and internally generate 19.2, 20, 24, 25, 26, 27,100 MHz?

Thanks,

11 months ago

+1 Kallikuppa Sreenivasa 11 months ago

TI__Guru**** 172624 points

Hello GR,

Thank you for the query.

I am reviewing you inputs and checking with the expert.

There are a few Errata related to serdes0 that could be referenced

https://www.ti.com/lit/er/sprz457h/sprz457h.pdf

Regards,

Sreenivasa

+1 -DK- 11 months ago

TI__Mastermind 27890 points

Q1: Yes, the EVM is operating in HCSL mode. HCSL clocking is required when operating in clock-input mode.

Q2: Yes, this SoC can source the 100MHz PCIe bus clock. Please note that this only applies to PG2.0. Refer to the silicon errata for more details.

Q3: This table is SerDes specific It means that the SerDes itself can operate as-described when provided any one of clock frequencies, but in the case of AM64xx, the only supported frequencies are 25MHz (internally clocked) and 100MHz (externally clocked).

0 GR 11 months ago in reply to -DK-

Expert 2961 points

Hello DK,Sreenivasa,

Thanks for your information.

I understand.

Best regards,

0 Kallikuppa Sreenivasa 11 months ago in reply to GR

TI__Guru**** 172624 points

Hello GR,

Thank you for the note,

Regards,

Sreenivasa

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AM6442: Serdes input clock (SERDES0_REFCLK)