This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

66AK2E05: What is the meaning of 1-Bit ECC Error Address Log Register (ONE_BIT_ECC_ERR_ADDR_LOG)?

Part Number: 66AK2E05

Hi,

We test the ECC with 1-bit error and observe 1-Bit ECC Error Address Log Register (ONE_BIT_ECC_ERR_ADDR_LOG).

From my understanding, this register will tell us which address has an bit error.

But test showed different result. So it really confuse us. We are in the third part company to do test. So this issue is urgent. Please help to give us ideas.

Inject error to 0xbeffff00,register value is 1f7fff80

Inject error to  0xbeffffff ,register value1f7fffe0

Inject error 0x90000000 ,register value08000000

Regards

Zekun

  • Zekun,

    Sure. Let me look at it and get back.

    Would you please give the link of your application notes, from which you posted the screenshot?

    Regards

    Shankari G

  • Zekun,

    Which application notes you refer for 66Ak2E05?

    I do not find the details of your screenshot in the EMIF app notes.

    --

    The appropriate app notes for EMIF NAND interface for 66AK2E05 is https://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf

    Page no: 29

    --

    3.7 ECC Support

    For data integrity purposes, NAND Flash supports ECC. EMIF16 supports 1-bit ECC calculation for up to 512 Bytes and 4-bit ECC calculation for up to 518 Bytes. 1-bit ECC calculation for NAND device connected to a specific chip select is set off by writing a ‘1’ to the CSN_ECC_START bit of the NAND Flash Control Register (NANDFCR). 1-bit ECC calculation for each chip select is independent of other chip selects. Once the 1-bit ECC is calculated for a chip select, it can be read from the corresponding chip select’s NAND Flash 1-bit ECC Register. Reading this register clears the CSN_ECC_START bit. Software is responsible for initiating the ECC calculation before starting to write or read data from the NAND Flash. It is also the responsibility of the software to read the calculated 1-bit ECC from the NAND Flash 1-Bit ECC register for the corresponding chip select after writing or reading the required number of data bytes from the NAND Flash. If the software writes or reads greater than 512 bytes before reading the NAND Flash ECC register, the value of the 1-bit ECC will be incorrect. Figure 3-3 shows how 1-bit ECC calculation is performed on a 512 Byte block of data for an 8-bit NAND Flash device.

    Refer figure 3-3 in https://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf

    In the figure, p1e through p4e are column parities and p8e through p2048e are row parities. This algorithm can be easily extended for 16-bit NAND device. For 16-bit device, column parities will run from p1e through p8e whereas row parities will run from p16e through p2048e. Note that the above figure applies only for 512 Byte data. To calculate 1-bit ECC for 8-bit NAND device for data less than 512 Bytes, the corresponding parities must be ignored. For example, for 256 Bytes of data, p2048e and p2048o are unnecessary and should be discarded. Similarly, for 128 Bytes, discard p1024e, p1024o, p2048e and p2048o.

    Regards

    Shankari G

  • Hi Shankari

     I refer to this one: DDR3 Memory Controller for KeyStone II Devices User's Guide (Rev. C)

    you can search on ti.com.

    I read your reply but still can not understand the scenario or my experiment. 

    Can you read the guide I mentioned?

    Regards

    Zekun

  • Zekun,

    Yes, I read the DDR3 app notes.

    Your understanding is right.

    1-Bit ECC Error Address Log Register  - has the address of the memory ( SDRAM) in which the value has 1 bit ecc error.

    Actually it stores two addresses of the first two - 1 bit ecc errors.

    When you write 0x1 to it, it will give you the second address ....that is..... the next address in which the value has 1 bit ecc error.

    For example, if the same address has two - 1 bit ecc errors, though you write 0x1 to it, it will again show the same address as the next address.

    I hope this explanation helps!

    ---

    Additional info on page no: 32 https://www.ti.com/lit/ug/spruhn7c/spruhn7c.pdf

    2.16.1.2 Logging 1-bit ECC Error Address For 1-bit ECC error, the controller logs the starting address of the SDRAM burst in an internal 2-deep address FIFO. This internal FIFO stores the first two 1-bit ECC errors. The 1-Bit ECC Error Address Log register will display the address on top of the internal FIFO. Software must write a 0x1 to the 1-bit ECC Address Log register to pop the FIFO and display the next address stored. The FIFO will be loaded with the address for the next 1-bit ECC error if it is not full. It must be noted that no address comparison will be performed, i.e., if a single address has ECC errors back-to-back, that address will be logged twice

    Regards

    Shankari G

  • Hi Shankari

    I understand the process of this register. 

    Here is our one experiment:

    Inject error to 0xbeffff00,register value is 1f7fff80

    Seems this register value 1f7fff80 has no relationship with the 0xbeffff00?

    Is there any Virt to Phy transition that led to this.

    Regards

    Zekun

  • Zekun,

    Is there any Virt to Phy transition that led to this.

    May be yes. Please check your configuration.

    Regards

    Shankari G