Other Parts Discussed in Thread: TDA4VH
Tool/software:
#1. On TDA4VH-EVM Schematic, on page 39, the PCIe clock impedance is 100ohm, but on page 70, it is 85ohm, which is typo? I think the differential clock impedance should be 100ohm.
#2. From spracp4 (Jacinto 7 High speed interface layout guidelines), PCIe differential clock impedance is 85ohm, data line is 100ohm, why not use same impedance? Is it PCIe specification/standard defined the parameter? or TI designed as it?
#3. As shared one PCIe connector(J14) have unique impedance on all pins, how to balance the layout impedance and connector impedance?