TMS320C6655: Tms320c6655

mounika arajala

Part Number: TMS320C6655

Tool/software:

Im using upp protocol for communication between fpga and c6655 . But im facung an erri error in ypisr register . Which is internal bus error. I think it is due to wrong pll configuration. Can u give some insight into how to do it for upp module clock.

3 months ago

0 Shankari G 3 months ago

TI__Mastermind 23875 points

Mounika,

We can find the uPP user guide here : - https://www.ti.com/lit/ug/spruhg9/spruhg9.pdf

In the MCSDK - Multicore software development kit - Software Package provided by TI may have some sample code for uPP.

please have a look at the configuration used in the sample code.

https://www.ti.com/tool/BIOSLINUXMCSDK

Regards

Shankari G

0 mounika arajala 3 months ago in reply to Shankari G

Prodigy 210 points

Hi Shankari,

The exact error im getting is erri bit in uPP Interrupt Raw Status Register (UPISR), which states internal bus error,

It would be helpful if you can share more on that.

0 mounika arajala 3 months ago in reply to mounika arajala

Prodigy 210 points

The problem we are facing is erri error in upisr register of upp like I mentioned early, I assume this is due to module clock which is going to upp is wrong. Beacuse the frequency we are getting is 166 MHz (sysclok 1000MHz/6)= 166 MHz) which is the frequency for emac (dspclock /6 )

Since by default both the upp and emac are in same low priority i think its happening like this, By changing the upp priority to urgent will this issue be solved or du you have any other suggestions or any other configurations need to be done inorder to solve the erri bus error issue.

Thanks