[FAQ] AM62x, AM64x, AM243x, Custom board hardware design – How to handle Used / Unused Pins / Peripherals and add pullup or pulldown ? (e.g. GPIOs, SERDES, USB, CSI, MMC (eMMC, SD-card), CSI, OLDI, DSI, CAP_VDDSx, .....)

Hi Board designers, 

Handling of the Used IOs or Peripherals and Unused IOs or Peripherals depends on the family of processors. 

The Following documents could be references

Device specific data sheet 

Device specific Errata 

Hardware Design Guide for family of devices 

Schematic Design and Review Checklist for family of devices 

These documents are available on the device specific product folder on TI.com. The product folder has many ore documents and tools that makes designing customer board simpler.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1455706/faq-am625-am623-am625sip-am620-q1-am625-q1-design-recommendations-custom-board-hardware-design---custom-board-schematics-self-review

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1456132/faq-am62a3-am62a7-am62a7-q1-am62a3-am62a3-q1-am62d-q1-design-recommendations-custom-board-hardware-design---custom-board-schematics-self-review

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1456130/faq-am62p-am62p-q1-design-recommendations-custom-board-hardware-design---custom-board-schematics-self-review

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1456123/faq-am6442-am6441-am6422-am6421-am6412-am6411-am243x-design-recommendations-custom-board-hardware-design---custom-board-schematics-self-review

if you have any questions or not able to find the right collateral, reach out to TI support over E2E.

The assigned TI expert can point you to the required collaterals and also provide additional guidance.

Additional references

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1337814/faq-am625-am623-am62a-am62p-design-recommendations-commonly-observed-errors-during-custom-board-hardware-design-soc-unused-peripherals-and-ios

Regards,

Sreenivasa

Additional inputs for Decoupling caps on CAP_VDDSx

Customer's asking what will happen if the decoupling caps on the CAP* nets below are not installed correctly? Will the device's behavior be well defined in this case (i.e. fail to boot etc) or would it be more sporadic based on operating mode? They are preparing manufacturing test definition and wondering about scenarios such as

DNP incorrectly.  
One or more of the caps are damaged due to handling and result in:
open
short
Is there any defined behavior for wrong values  of the capacitors that can be captured in testing?
Refer below FAQ

e2e.ti.com/.../4747088

Regards,

Sreenivasa

Additional inputs for handling RSVD pins 

If these signals are short-circuited, what will happen? I am thinking of cases such as a short circuit on each terminal in terms of functional safety. If there is no error in the functional test, there is no issue with the shorted RSVD pins or we don't have any shorts?

 Most of the reserved pins are analog test pins which are not driven during normal operation. These pins should always be in normal operation mode in a customer’s system since we do not allow customers to access the test functions associated with the analog test pins. Therefore, we do not anticipate an issue if they were accidently shorted to an adjacent ball.
This comment does not give customers permission to connect any signal traces to these pins.
There could be an issue if these pins were shorted to a power supply of higher potential. For example, a 1.8V power rail may be connected to a 3.3V power source via the pin’s ESD clamp circuit if one of the pins were shorted to 3.3V. In this case, the internal clamp diode would be forward biased and the higher potential would flow through the clamp diode and raise the potential applied to the 1.8v power rail. This could potentially create multiple EOS issues for the device.

Regards,

Sreenivasa

Additional inputs on selecting pulls (pullup or pulldown) for LVCMOS IOS

Customer is using 100K pulls. Given the below leakage current, is this a concern. Should customer be reducing the pull value?
IIN Input Leakage Current.
VI = 3.3 V or VI = 0.0 V ±10 μA
Which IO cell? Pull-up or pull-down?
These are SPI interfaces, emulated I2C interfaces ( not sure if they used as I2C since this goes to a connector) and IOs switching FET to indicate fault or for LEDs
LVCMOS IOs. Customer has used pullup as well as pulldown for different IOs. Not sure if I answered your query.

The customer should be validating these types of things based on their custom system design.
They need to select a resistor that is able to hold the signal above the steady-state high (VIHSS) or below the steady-state low (VILSS) based on the signals worst-case combination of leakage, which will be the sum of the max leakage of all attached devices.
For example, let’s assume they only connect our device to a single UART device that has a max leakage of 5uA when operating at 1.8V. The worst-case leakage would be 10uA + 5uA = 15uA. VIHSS for the LVCMOS IO cell operating at 1.8V is 0.85 x VDD = 1.53V. A pull-up resistor value would need to be at less than 18k ohms to hold the voltage above 1.53V for a worst-case leakage of 15uA. I would suggest they use a value that is less than 18K ohm for this example.

In this example, one end of the resistor is connected to VDD and the other to the signal. The voltage across the resistor must be less than 1.8V – 1.53V = 0.27V to maintain the proper steady-state VIHSS level. If the signal had a total of 15uA of leakage to ground the max voltage drop allowed across the resistor is 0.27V when the 15uA of current is flowing from VDD through the resistor to the ground. Therefore, the resistor would need to be less than 0.27V/15uA = 18k ohms.

Which IO cell? Pull-up or pull-down?
You asked me about the IO cell. Not sure on the reason. Any thoughts please.
I tried to find myself, looked at all the IO cell specs and all of them seem to specify ±10 μA
Because the VIHSS and VILSS values are different for the different IO types and if an internal pull is turned on the internal pull values are different. The leakage due to an internal pull being turned on is not included in the Input Leakage Current parameter values.

Are the VIHSS and VILSS value changes associated with the IO type and TI specific or based on JEDEC standards?

JEDEC does not define VIHSS or VILSS parameters.
The voltage limits defined by these parameters are specific to the IO design and operating voltage. The signal voltage needs applied to our input buffers must be above VIHSS or below VILSS when the signal is held in a steady-state condition. These parameters are needed to limit the shoot-through current that flows from VDD through the input buffer to VSS when the signal voltage is not pulled all the way to VDD or VSS. Staying above VIHSS or below VILSS will minimize the shoot-through current when the signal is not toggling. Too much exposure to shoot-through current has a chance of damaging the input buffer. The shoot-through current peaks to its maximum when the signal voltage is about VDD/2, and drops off very quickly as the signal voltage approaches either VDD or VSS. This is why we must limit the input slew rate, to minimize the time the signal voltage is in the mid-supply region. The shoot-though current drops low enough that it will not cause any long-term reliability issues when the signal voltage is above VIHSS or below VILSS. In some cases, the VIHSS and VILSS limits are the same as the JEDEC VIH and VIL limits.

The standard JEDEC VIH and VIL limits define the DC limits associated with valid logic states. The TI VIHSS and VILSS limits define steady-state DC limits required to ensure long-term device reliability.

Data sheet reference

Electrical Characteristics

IIN  Input Leakage Current for different IO types (LVCMOS, SDIO, Open drain and other IO types as applicable)

Regards,

Sreenivasa

Additional inputs on pulls used on the SK or EVM 

TI recommendations are being provided as good starting point for the custom board designer, but the custom board designer must validate all TI recommendations are appropriate for their specific board and end equipment implementation

Regards,

Sreenivasa