DMA action via the GPMC in AM3703 device.

We have an AM3703 device connected to a FPGA via the GPMC interface. In the FPGA, packets are available with variable packet lengths between 47 and 500 DWORDs (32-bit). We want to transfer these packets as fast as possible to the ARM processor. We have 2 possible methods to transfer the packet to the ARM processor:

Italic indicates a question.

Method 1:

1. The length of the packet is stored into a FPGA register which is available for the ARM processor.
2. Interrupt  to the ARM processor indicating that a new packet is available in the FPGA.
3. ARM processor will handle interrupt and will read the length of the packet via the FPGA register.
4. ARM processor will initiate a DMA transfer to transfer the packet to the DDR2 memory (SDRC interface). The GPMC can only handle bursts of 4, 8 or 16 WORDs (16-bit). How will handle the sDMA these larger burst sizes (split into smaller bursts)?

Method 2 (based on old hardware platform with another processor):

1. The ARM processor will initiate a DMA transfer with a length of e.g. 512 DWORDS.
2. If a complete packet is available in the FPGA, the FPGA will start the DMA via the DMA request line.
3. The DMA will transfer the packet to the DDR2 memory (SDRC interface). Note that the DMA transfer is not completely finished because not all 512 DWORDS are transferred.
4. FPGA indicates to the ARM processor the end of the packet. Is it possible to hold a (not complete) DMA transfer via an external signal? 
5. ARM processor will break DMA transfer and will initiate a new DMA transfer. Is it possible to break a (not complete) DMA transfer via an external signal or via software? 

Are there another efficient methods to transfer the packets?