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DRA821U: Hyperbus initialization

Kari Keinanen
Prodigy 10 points
Part Number: DRA821U

Tool/software:

Our J7200EVM evaluation module initializes hyperbus in SPL bootloader, especially MCU_FSS0_HPB_SS_CFG-register SDL_LOCK bit is set properly and calibration succeeds (based on debug prints).

But in our custom board, hyperbus calibration fails.

We have FPGA-chip emulating Hyper-RAM.

SPL bootloader doesn't probe hbmc-am654 driver (like it does in evaluation module) and the driver is only run after SPL in u-boot where calibration fails with "Error handler, esr 0xbf000002"

Part of device-tree configuration:

&wkup_pmx0 {

  mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
    pinctrl-single,pins = <
      J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* B6, MCU_HYPERBUS0_CK */
      J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* C8, MCU_HYPERBUS0_CKn */
      J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* D6, MCU_HYPERBUS0_CSn0 */
      J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* D7, MCU_HYPERBUS0_RESETn */
      J721E_WKUP_IOPAD(0x38, PIN_INPUT, 2) /* C6, MCU_HYPERBUS0_RESETOn */
      J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 2) /* D5, MCU_HYPERBUS0_INTn */
      J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* B7, MCU_HYPERBUS0_RWDS */
      J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* D8, MCU_HYPERBUS0_DQ0 */
      J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* C7, MCU_HYPERBUS0_DQ1 */
      J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* C5, MCU_HYPERBUS0_DQ2 */
      J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* A5, MCU_HYPERBUS0_DQ3 */
      J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* A6, MCU_HYPERBUS0_DQ4 */
      J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* B8, MCU_HYPERBUS0_DQ5 */
      J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* A8, MCU_HYPERBUS0_DQ6 */
      J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* A7, MCU_HYPERBUS0_DQ7 */
>;
  };
}

&cbass_mcu_wakeup {

  fss: syscon@47000000 {
    compatible = "syscon", "simple-mfd";
    reg = <0x00 0x47000000 0x00 0x100>;
    #address-cells = <2>;
    #size-cells = <2>;
    ranges;

    hbmc_mux: hbmc-mux {
      compatible = "mmio-mux";
      #mux-control-cells = <1>;
      mux-reg-masks = <0x4 0x2>; /* HBMC select */
    };

    hbmc: hyperbus@47034000 {
      compatible = "ti,am654-hbmc";
      reg = <0x00 0x47030000 0x00 0xc>,
<0x00 0x47034000 0x00 0x100>,
<0x05 0x00000000 0x01 0x0000000>;
      power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
      clocks = <&k3_clks 102 0>;
      assigned-clocks = <&k3_clks 102 5>;
      assigned-clock-rates = <333333333>;
      #address-cells = <2>;
      #size-cells = <1>;
      mux-controls = <&hbmc_mux 0>;
    };

  };
};

&hbmc {
  status = "okay";
  pinctrl-names = "default";
  pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
  ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */
<0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */

  flash@0,0 {
    compatible = "cypress,hyperflash", "cfi-flash";
    reg = <0x00 0x00 0x4000000>;

    partitions {
      compatible = "fixed-partitions";
      #address-cells = <1>;
      #size-cells = <1>;

      partition@0 {
        label = "hbmc.tiboot3";
        reg = <0x0 0x100000>;
      };

      partition@100000 {
        label = "hbmc.tispl";
        reg = <0x100000 0x200000>;
      };

      partition@300000 {
        label = "hbmc.u-boot";
        reg = <0x300000 0x400000>;
      };

      partition@700000 {
        label = "hbmc.env";
        reg = <0x700000 0x40000>;
      };

      partition@800000 {
        label = "hbmc.rootfs";
        reg = <0x800000 0x3800000>;
      };
    };
  };
};

&hbmc {
  bootph-pre-ram;

  flash@0,0 {
    bootph-pre-ram;
  };
};

&hbmc_mux {
  bootph-pre-ram;
};

Best regards, Kari

  • 0
    TI__Guru*** 149350 points

    Hi,

    Can you trace the exact instruction that causes the above error by adding debug logs?

    Also which SDK version is being used and share your changes in the patch format for us to review.

    Best Regards,

    Keerthy 

  • 0 in reply to Keerthy J
    Prodigy 10 points

    Hi.

     

    Our u-boot is based on https://git.ti.com/cgit/ti-u-boot/ti-u-boot/commit/?h=ti-u-boot-2023.04&id=9390b636e8e292a85f236b4f1c70feb0ad8299cc, build is using yocto kirkstone.

    Evaluation module initializes hyperbus already in SPL, but in our custom board we first need to load FPGA-image and thinking hyperbus initialization bit later in 72 u-boot or Linux.

    I was hoping to get detailed steps what needs to be done to get MCU_FSS0_HPB_SS_CFG-register SDL_LOCK bit set.

     

    Best regards,

    Kari

  • 0 in reply to Kari Keinanen
    TI__Guru*** 149350 points

    Hi Kari,

    Kari Keinanen said:
    Evaluation module initializes hyperbus already in SPL, but in our custom board we first need to load FPGA-image and thinking hyperbus

    Who is loading the fpga image? Is this something done in parallel? If yes then can we consider adding a delay in SPL?

    Best Regards,

    Keerthy 

  • 0 in reply to Keerthy J
    Prodigy 10 points

    Hi.

    We are loading FPGA image via spi-bus in u-boot (no parallel loading) and we managed to get the calibration working and SDL_LOCK bit is set.

    We disabled calibration in u-boot hbmc-am654.c driver and made own calibration code after FPGA image is loaded, code below:

    writel(0xC, 0x42000120); // WKUP_PSC0_PTCMD
    writel(0x80000010, 0x47034020); // MCU_FSS0_HPB0_MC_MCR_y
    writel(0x221001, 0x47034030); // MCU_FSS0_HPB0_MC_MTR_y

    And then reading 64 * 64 bytes until SDL_LOCK bit is set, this works.

    With TI evaluation board hyperbus seems to be working only with 20MHz, in our custom board calibration fails with 20MHz (so we are using 100MHz).

    However, now we are getting some read errors in Linux...we don't know why.

    Best regards,

    Kari

  • 0 in reply to Kari Keinanen
    TI__Guru*** 149350 points

    Hi Kari,

    I am assuming no errors seen on the TI EVM. Can you share the error codes/logs? I can check with our hyperbus expert.

    Thanks,

    Keerthy 

  • 0 in reply to Keerthy J
    Prodigy 10 points

    Hi, Keerthy.

    With TI EVM, no errors with 20MHz, but with 100MHz we get "[ 205.134742] SError Interrupt on CPU0, code 0x00000000bf000002 -- SError" in Linux when trying to access the memory.

    With our custom board, error happens occasionally (about 5 errors per 100 test rounds, one test round includes test application which writes and reads 64 bytes 10000 times to memory via hyperbus, then power reset and another test round...).

    It is only memory read which returns some value, read value is just different what we expect.

    How to check error code as we only get some value from memory ?

    -Kari-

  • 0 in reply to Kari Keinanen
    TI__Guru*** 149350 points
    Kari Keinanen said:

    It is only memory read which returns some value, read value is just different what we expect.

    Okay understood. It's not read function returning error codes. 

    Kari Keinanen said:
    but with 100MHz we get "[ 205.134742] SError Interrupt on CPU0, code 0x00000000bf000002 -- SError" in Linux when trying to access the memory

    This is something we have not validated with.

    - Keerthy

  • 0 in reply to Keerthy J
    Prodigy 10 points

    Could you please validate 100MHz ?

    We would really appreciate this information.

    -Kari-

  • 0 in reply to Kari Keinanen
    TI__Guru*** 149350 points

    Kari,

    I will consult with the expert internally. I will get back need week as the expert is unavailable this week. It will be good if you can check why 20M works on evm and fails on custom board.

    Best regards,

    Keerthy