AM625: How to set correct VDD_CORE & VDDA_DDR_PLL0 for LPDDR4

Hi Gibbs,

Thanks for reaching out. We will review the information and provide an update within the next 24-48Hrs.

Thanks,

Brenda

Hi,

Thanks for your patience. Please find the feedback below and let us know if there are any questions.

Gibbs Shih said:

Q1 : Because of ALW package do not have "VDDA_DDR_PLL0" pin,  This power rail is internally connected to VDD_CORE in the ALW package. So we don't care VDDA_DDR_PLL0 pin connection in ALW  package, Am I correct?

As noted in the AM62x datasheet, VDDA_DDR_PLL0 is only available on the AMC package. This power rail is internally connected to VDD_CORE in the ALW package.

Gibbs Shih said:

Q2 : If we use TPS6521902, the VDD_CORE of AM62x is 0.75V only, Am I correct?

Correct. TPS6521902 NVM has Buck1 configured to output 0.75V.

Gibbs Shih said:

Q3 : I found TPS6521908 is also another choice for LPDDR, and VDD_CORE is 0.85V, but its LDO2 is disable. What's kind of user case for TPS6521908?

TPS6521908 is another option for customers who want to supply VDD_CORE with 0.85V instead of 0.75V. As noted in the processor datasheet, VDD_CORE and VDDR_CORE are expected to be powered by the same source so they ramp together when VDD_CORE is operating at 0.85V. In this scenario, we don't need to configure an LDO in the PMIC to supply 0.85 because Buck1 can supply both. This is why LDO2 is disabled. 

Thanks,

Brenda