AM62P: When Bringping AM62P, the serial port information is hang up in the "Trying to boot from MMC2".

The DDR configuration file is as follows:

/**
 * These arguments were used when this file was generated. They will be automatically applied on subsequent loads
 * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
 * @cliArgs --device "AM62Px" --part "Default" --package "AMH" --product "Processor_DDR_Config@0.10.02"
 * @v2CliArgs --device "AM62P" --package "FCBGA (AMH)" --variant "AM62P54-M" --product "Processor_DDR_Config@0.10.02"
 * @versions {"tool":"1.21.0+3721"}
 */

/**
 * Import the modules used in this configuration.
 */
const DDRSS = scripting.addModule("/DDRSS");

/**
 * Write custom configuration values to the imported modules.
 */
DDRSS.lpddr4.$name                       = "sitara_lpddr4_DDRSS_LPDDR40";
DDRSS.lpddr4.config_dram_tRPab_tCK       = 4;
DDRSS.lpddr4.config_dram_tRFCab_ns       = 130;
DDRSS.lpddr4.config_dram_tRFCpb_ns       = 60;
DDRSS.lpddr4.config_dram_tRPpb_tCK       = 4;
DDRSS.lpddr4.config_dram_tVREFcashort_ns = 80;
DDRSS.lpddr4.config_dram_tWR_tCK         = 6;
DDRSS.lpddr4.config_dram_tRASmax_ns      = 70200;
DDRSS.lpddr4.system_cfg_periodic_zqcal   = "Enabled - 256ms period";
DDRSS.lpddr4.system_cfg_dram_density     = 2;
DDRSS.lpddr4.system_cfg_periodic_train   = "Yes";
DDRSS.lpddr4.system_cfg_dram_ranks       = 1;

hi

    By opening the debug print of the DDR driver, the serial port print is as follows:

Wang, from the schematic, it looks like you are using a 2 rank device, but you have only selected one rank in the configuration.  Please change back to 2 ranks and try again.

Also, is the bit swizzling on your board the same as on the AM62P EVM?

Regards,

James

Hi James, 

from the datasheet, the NANYA lpddr4 is single rank device, and we also try change the Rank to 2(density to 1), but it can't help, and the fail log is same.

the bit swizzling is same as AM62P EVM. also we have tried to reduce the frequency to 2666, but it can't work too.

BR,

Biao 

Hi James, 
After the u-boot apply 0001-regdump-patch-files.patch  patch .The output log of the serial port is as follows:

ddr_regdump.log

Hi James,

Can you help check the regdump from customer? can you give some adjust suggestion to us? I have let customer rework a board to Micron 1GB ddr, and use below config, but it can't work too. will stuck at boot from mmc2 as well. 

all (4).zip

BR,

Biao 

Hi James, 
   When the terminal serial port is stuck, connect through CCS and check that the data at address 0x80000000 is all 0. The data of DDR cannot be changed through CCS.The screenshot of CCS is as follows:

Hi James,

If you need any more info pls let us know, thanks a lot for your support.

BR,

Biao

Hi Biao, sorry for the late reply.  I reviewed the schematics, and the customer may have the CS signals connected incorrectly, but i need to see the connection on the memory side to confirm.

Notice on this schematic from the EVM, the top two signals correspond to channel A, and the bottom 2 signals correspond to channel B.  If you are using a single channel device, you would connect CS0_A and CS0_B

But in the customer schematic, as least from the signal labels, it appears they have connected CS0 channel A/B signals at the top, and CS1 channel A/B signals at the bottom.  Please send the memory side of the schematic so i can confirm.

If this is the case, they would only be able to use this device as a 16-bit device, and they would have to re-build their boards to update the signal connectivity to be able to get the full 32bit data width

Regards,

James

Hi James, 

Actually, Nanya said this is Dual rank device, I will upload the full schematic to you. 
BR,

Biao

Hi James,

full schematic sent to via email.

BR,

Biao