TDA4VH-Q1: TDA4VH: Cacheable for PCIe BAR ?

Tool/software:

Hi expers,

Can PCIe BAR space be configured as cacheable while user mmap？

static int pci_endpoint_test_mmap(struct file *file, struct vm_area_struct *vma)
{
	struct pci_endpoint_test *test = to_endpoint_test(file->private_data);
	size_t size = vma->vm_end - vma->vm_start;
	u64 phyaddrstart = ((u64)vma->vm_pgoff) << PAGE_SHIFT;
	struct pci_dev *pdev = NULL;
	struct device *dev = NULL;
	bool remotecheck;
	bool localcheck;
	
	if(!test || !test->pdev){
		return -EINVAL;
	}

	pdev = test->pdev;
	dev = &pdev->dev;

	remotecheck = pci_endpoint_memory_remote_check(test,phyaddrstart,size);
	localcheck = pci_endpoint_memory_local_check(test,phyaddrstart,size);
	
	if(!remotecheck && !localcheck){
		dev_err(dev, "Mmap memory not valid 0x%llx !!! \n",phyaddrstart);
		return -EPERM;;
	}

	if (!(file->f_flags & O_SYNC)) {
		dev_warn(dev, "NoCache cfg for PCIe memory !!! \n");
		file->f_flags |= O_SYNC;
	}

	//nocache normal (default)
	//vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);

	if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 
					size, vma->vm_page_prot)) {
		return -EAGAIN;
	}

	return 0;
	
}

When PCIe bar is configured as cacheable, writing and reading data are inconsistent. Do we need additional configuration?

QuanLi

Thanks