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AM6442: R5F core : GPIO peripheral clock frequency query

Part Number: AM6442

Tool/software:

Hello,

I am using mcu_plus_sdk_am64x_09_01_00_41 and have written code to measure GPIO write and read times.

The R5F core clock is set to 800 MHz, and the GPIO peripheral clock (GPIO0_VBUS_FICLK) is set to 125 MHz.

Below is the code flashed to the R5F core. The waveforms were observed on an oscilloscope:

    gpioBaseAddr = (uint32_t) AddrTranslateP_getLocalAddr(GPIO_LED_BASE_ADDR);
    pinNum       = GPIO_LED_PIN;
    GPIO_setDirMode(gpioBaseAddr, pinNum, GPIO_LED_DIR);

    gpioBaseAddr1 = (uint32_t) AddrTranslateP_getLocalAddr(OUTPUT_GPIO_BASE_ADDR);
    pinNum1       = OUTPUT_GPIO_PIN;
    GPIO_setDirMode(gpioBaseAddr1, pinNum1, OUTPUT_GPIO_DIR);

    uint32_t                regIndex1, regVal1;
    volatile CSL_GpioRegs*  hGpio = (volatile CSL_GpioRegs*)((uintptr_t) gpioBaseAddr1);
    regIndex1 = GPIO_GET_REG_INDEX(pinNum1);
    regVal1 = GPIO_GET_BIT_MASK(pinNum1);

    uint32_t                regIndex, regVal;
    volatile CSL_GpioRegs*  hGpio1 = (volatile CSL_GpioRegs*)((uintptr_t) gpioBaseAddr);
    regIndex = GPIO_GET_REG_INDEX(pinNum);
    regVal = GPIO_GET_BIT_MASK(pinNum);

    while(1)
    {
        CSL_REG32_WR(&hGpio->BANK_REGISTERS[regIndex1].SET_DATA, regVal1);
        CSL_REG32_WR(&hGpio->BANK_REGISTERS[regIndex1].CLR_DATA, regVal1);
        CSL_FEXTR(hGpio1->BANK_REGISTERS[regIndex].IN_DATA, regVal, regVal);
        CSL_REG32_WR(&hGpio->BANK_REGISTERS[regIndex1].SET_DATA, regVal1);
        CSL_REG32_WR(&hGpio->BANK_REGISTERS[regIndex1].CLR_DATA, regVal1);

    }

From the waveforms, we observed the following timings:

  • GPIO High time: ~210 ns
  • GPIO Low time: ~210 ns
  • GPIO Read time: ~210 ns

Could you please confirm if these timings are correct?

Additionally, I would like to know if it is possible to increase the GPIO peripheral clock frequency beyond 125 MHz to achieve a time lower than 210 ns. If it is possible to increase the peripheral clock frequency, what are the steps to change it?

Can we increase the PLL0_hsdiv0 value more than 500MHz? And what is the maximum value of PLL0_hsdiv0 is allowed?

Thank you,

Pratibha