TDA4VH-Q1: TDA4VH

Hello,

Our published rating of DMIPS for the A72 is based on running the dhrystone program.  The only variation is we use is with and without compiler inlining as its common to see others publish non-inlined numbers.  You can see the method used to get DMIPs in many areas, I'll attach an ARM application note link which clearly describes what DMIPS is : https://developer.arm.com/documentation/105958/latest/ .  The adhoc formula you cite is not one we use. The predictive power of Dhrystone is extremely low in any modern A/R class CPU.  Typical application work loads you will run on these cores likely do not resemble Dhrystone MIPS at all (fully L1 cache resident procedural only execution). For an A/R core maybe its most useful in looking at power draw.  On A/R cores you should use many benchmarks which span a lot of use cases.  Maybe for a Cortex-M its more useful  A bit more useful series to consider is EEMBC coremark and coremark-pro.

If you look at this E2E thread you will get a look at how to TDA4 had its A72 dhrystone measured.  https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1392814/am67-linux-sdk-dhrystone-benchmark-results/5330023#5330023 .  A dhrystone as much as anything else will depend on the compiler you are using and its flags, your results can swing easily by 400% with just SW changes.  You can find most all standard ARM cores values published on ARMs website.  As far as the DSP goes, benchmarking FLOPs or TOPs (depending on use case) more targets its usage.  I don't believe we publish a dhrystone value for the DSP but it would be straight forward to run (but not at all representative of its usage).

Hello,

As mentioned in below query we are using the TDA4VH board with Ti Linux SDK for software development. Currently we are utilizing the standard linux TOP command and the Perf tool within the SDK for making observations on CPU Load in % values. We checked in the Data sheer of the TDA4VH and could not find a formula to get the CPU load in DMIPS.

 TDA4VH-Q1: Formula for converting % CPU load to DMIPS - Processors forum - Processors - TI E2E support forums

As I have noticed in above link A72 can achieve around ~6 DMIPS/MHz. 

Could you please help us by conforming correct formula for convert % CPU load to DMIPS is that same as mentioned below?

DMIPS Utilized = (CPU utilization percentage) * (Maximum DMIPS rating of the CPU)

And please provide max DMIPS for all these cores -- A72, R5, M4, C7x and how to convert that DMIPS/MHz to DMIPS for TDA4 board with TI-linux and QNX also.

Hello,

Apologies for a slow re-reply.  As I mentioned above there is not a precise formula which converts CPU load to DMIPS. When Dhrystone is running the Linux top utility will show the cpu load at 100% as dhry will take all the available time for a single core.  What is really needed to predict application performance is to find the loop time for a typical application for a given core. Then use that for your capacity planning.  An analogy might help show why dhrystone is underpowered by itself for prediction... trying to use Dhrystone to predict performance of a big core is like trying to use the wheel-speed of a vehicle to predict how much weight (load) it can tow behind a given vehicle. The towing capacity for a motor bike (M4), car (R5), and tractor (C7) will be wildly different even though their wheel speed might be the same.   If you don't have your exact application to measure you can bundle a bunch of benchmarks per core and use that as a simple model.   I did run dhry (w/inline) on the TDA4VH-MCU-R5 and I got 1.9 DMIPS/MHz with GCC, and 2.1DMIPS/MHz with ARMCC.

DMIPS is a single core test.  So to convert DMIPS/MHz into DMIPS just multiple by MHz the core is set to run at.  Eg, for TDA4VH A72, the simple conversion is 6.25x2000x8=100,000.