PROCESSOR-SDK-J784S4: PROCESSOR-SDK-J784S4: Understanding memory section in FFTlib

MadhuBala E

Part Number: PROCESSOR-SDK-J784S4
Other Parts Discussed in Thread: FFTLIB

Tool/software:

I have a test application developed for computing the FFT for our custom raw data and the linker file for our test application is as follows,

Processor : J784s4_evm

Core : C7x_1

Here the memory address for L1 and L2 Ram is taken from the system_memory_map from the vision_apps.

In FFTLib lnk.cmd "ti-processor-sdk-rtos-j784s4-evm-09_02_00_05\fftlib_09_02_00_04\cmake\linkers\C7120\lnk.cmd" , the memory address given for L1 and L2 looks different , can you please comment on these addresses where these are used in the FFT library because I am facing issue while booting this test application from linux system which is clashing some how with the memory

MEMORY

{

#if defined(RTL_TEST)

L2SRAM (RWX) : org = 0x64E00000, len = 0xB200000

/* Temporary place holder for L1D*/

L1DSRAM (RWX): org = 0xA0000000, len = 0x004000

#else

L2SRAM (RWX) : org = 0x64E00000, len = 0xF800000

/* Temporary place holder for L1D*/

L1DSRAM (RWX): org = 0xA0000000, len = 0x004000

#endif

EXTMEM (RWX) : org = 0x80000000, len = 0x800000

}

Thanks

5 months ago

0 Brijesh Jadav 5 months ago

TI__Guru**** 449075 points

Hi Madhu,

Sorry, what issue are you facing? The addresses for both L2SRAM and L1D seems to be match in the above code snippet. Do you mean this is different from the code inside FFT_library example?

Regards,

Brijesh

0 MadhuBala E 5 months ago in reply to Brijesh Jadav

Intellectual 255 points

Hi Brijesh

Thanks for the reply , I am facing issue when I am running a test application that has this fft lib linked and above two memory sections are for test app and fft lib respectively.

I am running this test application on top of Linux OS by booting it using Sd card but I am facing boot failure issues because the standard fft lib memory section may be crashing with the linux memory section. Need to understand more about the fft lib memory section details

Thanks

Madhu

0 MadhuBala E 5 months ago in reply to MadhuBala E

Intellectual 255 points

Hi Brijesh

Additionally, I want to add Below is the linker_c7x_freertos.cmd file that we use for our test application.

--ram_model
-heap  0x20000
-stack 0x20000
--args 0x1000
--diag_suppress=10068 /* "no matching section" */
--cinit_compression=off
-e _c_int00_secure

MEMORY
{
    L2SRAM (RWX):   org = 0x64800000, len = 0x00070000
    L1DSRAM  (RWX): org = 0x64E00000, len = 0x004000   // 16kB, for J7
    MSMCSRAM (RWX): org = 0x70000100, len = 0x7fff00
}

SECTIONS
{
    boot:
    {
      boot.*<boot.oe71>(.text)
    } load > C7X_1_TEXT ALIGN(0x200000)
    .vecs       >       C7X_1_DDR_SPACE ALIGN(0x400000)
    .secure_vecs    >   C7X_1_DDR_SPACE ALIGN(0x200000)
    .text:_c_int00_secure > C7X_1_DDR_SPACE ALIGN(0x200000)
    .text       >       C7X_1_DDR_SPACE ALIGN(0x200000)

    .l1dmemory  >       L1DSRAM
    .l2dmemory  >       L2SRAM
    .bss        >       C7X_1_DDR_SPACE  /* Zero-initialized data */
    .data       >       C7X_1_DDR_SPACE  /* Initialized data */

    .cinit      >       C7X_1_DDR_SPACE  /* could be part of const */
    .init_array >       C7X_1_DDR_SPACE  /* C++ initializations */
    .stack      >       C7X_1_DDR_SPACE ALIGN(0x2000)
    .args       >       C7X_1_DDR_SPACE
    .cio        >       C7X_1_DDR_SPACE
    .const      >       C7X_1_DDR_SPACE
    .switch     >       C7X_1_DDR_SPACE /* For exception handling. */
    .sysmem     >       C7X_1_DDR_SPACE /* heap */

    GROUP:              >  C7X_1_DDR_SPACE
    {
        .data.Mmu_tableArray          : type=NOINIT
        .data.Mmu_tableArraySlot      : type=NOINIT
        .data.Mmu_level1Table         : type=NOINIT
        .data.Mmu_tableArray_NS       : type=NOINIT
        .data.Mmu_tableArraySlot_NS   : type=NOINIT
        .data.Mmu_level1Table_NS      : type=NOINIT
    }

    ipc_data_buffer:       > C7X_1_DDR_SPACE
    .benchmark_buffer:     > C7X_1_DDR_SPACE ALIGN (32) 
    .l2mem              (NOLOAD)(NOINIT) : {} > L2SRAM
    .l1mem              (NOLOAD)(NOINIT) : {} > L1DSRAM
    .l3mem              (NOLOAD)(NOINIT) : {} > MSMCSRAM
    .resource_table: { __RESOURCE_TABLE = .;} > C7X_1_EXT_D
    .sensorData    : {} align(128)     > SHARED_DDR_SPACE
}

As you can see, L1 and L2 are allocated for scratch memory, not for any loadable program or data segments. However, when we run our test executable on the j784s4_evm (where Linux boots from the SD card), we encounter the error mentioned earlier.

wtx loaded /lib/firmware/j784s4-c71_0-fw @ 0x0000000082000000: 10815944 bytes read in 477 ms (21.6 MiB/s)
Warning: Did not detect image signing certificate. Skipping authentication to prevent boot failure. This will fail on Security Enforcing(HS-SE) devices
"Error" handler, esr 0xbf000000
elr: 00000000808bed18 lr : 000000008086e388 (reloc)
elr: 00000000fff84d18 lr : 00000000fff34388
x0 : 0000000064e00000 x1 : 0000000000000000
x2 : 0000000000001800 x3 : 0000000000000140
x4 : 0000000000000000 x5 : 00000000000016c0
x6 : 0000000000000000 x7 : 0000000000e0c000
x8 : 0000000000000010 x9 : 0000000000000008
x10: 0000000000000008 x11: 00000000fde969e0
x12: 0000000000000000 x13: 0000000000000200
x14: 0000000000000004 x15: 0000000000000020
x16: 00000000fff2f854 x17: 0000000000000000
x18: 00000000fde85db0 x19: 0000000000000000
x20: 0000000082a4fbf0 x21: 0000000000000000
x22: 0000000082000000 x23: 00000000fde8a2c0
x24: 00000000fff8f3b8 x25: 0000000000000000
x26: 0000000064e00000 x27: 0000000000001800
x28: 0000000064e00000 x29: 00000000fde6f630

Code: d2800004 eb04005f 540000e1 d65f03c0 (f8236804)
Resetting CPU ...

resetting ...

It appears that our memory addresses are conflicting with the Linux boot process.

My question is why we have these L1 and L2 addresses in the lnk.cmd (located at /ti-processor-sdk-09_02_00/ti-processor-sdk-rtos-j784s4-evm-09_02_00_05/fftlib_09_02_00_04/cmake/linkers/C7120/lnk.cmd).

Along with that, I have the following questions:

The lnk.cmd file located at /ti-processor-sdk-09_02_00/ti-processor-sdk-rtos-j784s4-evm-09_02_00_05/fftlib_09_02_00_04/cmake/linkers/C7120/lnk.cmd seems to have incorrect addresses for L1 and L2. What does these temporary placeholders for the L1SRAM in DDR mean in this file?

#if defined(FLAT_MEM)
-heap  0x7C00000
-stack 0x20000
--args 0x1000

--diag_suppress=10068 // "no matching section"
--cinit_compression=off

MEMORY
{
#if defined(RTL_TEST)
  L2SRAM (RWX)  : org = 0x64E00000, len = 0xB200000
  /* Temporary place holder for L1D*/
  L1DSRAM  (RWX): org = 0xA0000000, len = 0x004000
#else
  L2SRAM (RWX)  : org = 0x64E00000, len = 0xF800000
  /* Temporary place holder for L1D*/
  L1DSRAM  (RWX): org = 0xA0000000, len = 0x004000
#endif
  EXTMEM (RWX)  : org = 0x80000000, len = 0x800000
}

SECTIONS
{
  .sram_start START(_sram_start) > L2SRAM NOINIT

  .kernel: {
    *.obj (.text:optimized) { SIZE(_kernel_size) }
  } > L2SRAM

  .kernel_data SIZE(_data_size)

  .text:            > L2SRAM
  .text:touch:      > L2SRAM
  .neardata:        > L2SRAM
  .rodata:          > L2SRAM
  .bss:             > L2SRAM
  .init_array:      > L2SRAM
  .far:             > L2SRAM
  .fardata:         > L2SRAM
  .neardata         > L2SRAM
  .rodata           > L2SRAM
  .data:            > L2SRAM
  .switch:          > L2SRAM
  .stack:           > L2SRAM
  .args:            > L2SRAM align = 0x4, fill = 0 {_argsize = 0x200; }
  .sysmem:          > L2SRAM
  .cinit:           > L2SRAM
  .const:           > L2SRAM START(const_start) SIZE(const_size)
  .pinit:           > L2SRAM
  .cio:             > L2SRAM
  .stack:           > L2SRAM
  .staticData       > L2SRAM
  .msmcData         > L2SRAM
  .ddrData          > L2SRAM
  .l1dmemory        > L1DSRAM
  .l2dmemory        > L2SRAM
   xdc.meta:        > L2SRAM, type = COPY
}

#else // not FLAT_MEM

-heap  0x70000   // 448 kB
-stack 0x4000    //  16 kB
--cinit_compression=off
--args 0x1000
--diag_suppress=10068 // "no matching section"

MEMORY
{
#if SOC == j784s4
  MSMC3SRAM_CINIT (RWX)   : org = 0x70000000, len = 0x000100
  MSMC3SRAM (RWX)         : org = 0x70000100, len = 0x1fff00
  MSMC3SRAM_STATIC   (RWX): org = 0x70200000, len = 0x200000
  MSMC3SRAM_DATACN   (RWX): org = 0x70400000, len = 0x300000
  MSMC3SRAM_PT       (RWX): org = 0x70700000, len = 0x100000
  MSMCSRAM (RWX)          : org = 0x68000000, len = 0x300000
#else
  MSMCSRAM_CINIT (RWX)  : org = 0x70000000, len = 0x000100
  MSMCSRAM (RWX)        : org = 0x70000100, len = 0x3fff00
  EXTMEM_STATIC   (RWX): org = 0x80000000, len = 0x2000000
  EXTMEM_DATACN   (RWX): org = 0x82400000, len = 0x400000
  EXTMEM   (RWX): org = 0x82800000, len = 0x400000
  EXTMEMPAGE (RWX): org = 0x82C00000, len = 0x200000
#endif // SOC
  L2SRAM   (RWX): org = 0x64800000, len = 0x080000   // for J7
  L1DSRAM  (RWX): org = 0x64E00000, len = 0x004000   // 16kB, for J7


}

SECTIONS
{
  .sram_start START(_sram_start) > L2SRAM NOINIT

  .kernel: {
    *.obj (.text:optimized) { SIZE(_kernel_size) }
  } > L2SRAM

  .kernel_data SIZE(_data_size)
  .l1dmemory        > L1DSRAM
  .l2dmemory        > L2SRAM
#if SOC == j784s4
  .text:            > MSMC3SRAM
  .text:touch:      > MSMC3SRAM
  .text:_c_int00:   > MSMC3SRAM_CINIT
  .neardata:        > MSMC3SRAM
  .rodata:          > MSMC3SRAM
  .bss:             > MSMC3SRAM
  .init_array:      > MSMC3SRAM
  .far:             > MSMC3SRAM
  .fardata:         > MSMC3SRAM
  .neardata         > MSMC3SRAM
  .rodata           > MSMC3SRAM
  .data:            > MSMC3SRAM

  .data:pte:pte_lvl1_0000000000000000 > MSMC3SRAM_PT
  .data:pte:pte_lvl0 > MSMC3SRAM_PT
  .data:pte:pte_lvl2_40000000 > MSMC3SRAM_PT
  .data:pte:pte_lvl2_80000000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_64800000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_64E00000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_64D00000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_64D20000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_64D40000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_64D60000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_64D80000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_64DA0000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_64DC0000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_64DE0000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_70000000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_70200000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_70400000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_70600000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_80000000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_80200000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_80400000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_80600000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_80800000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_80A00000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_80C00000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_80E00000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_81000000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_81200000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_81400000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_81600000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_81800000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_81A00000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_81C00000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_81E00000 > MSMC3SRAM_PT

  .switch:          > MSMC3SRAM
  .stack:           > MSMC3SRAM
  .args:            > MSMC3SRAM align = 0x4, fill = 0 {_argsize = 0x200; }
  .sysmem:          > L2SRAM
  .cinit:           > MSMC3SRAM
  .const:           > MSMC3SRAM START(const_start) SIZE(const_size)
  .pinit:           > MSMC3SRAM
  .cio:             > MSMC3SRAM
  .stack:           > MSMC3SRAM
  .ddrData          > MSMC3SRAM_DATACN
  .staticData       > MSMC3SRAM_STATIC
  .msmcData         > MSMCSRAM
   xdc.meta:        > MSMC3SRAM, type = COPY
#else
  .text:            > MSMCSRAM
  .text:touch:      > MSMCSRAM
  .text:_c_int00:   > MSMCSRAM_CINIT
  .neardata:        > MSMCSRAM
  .rodata:          > MSMCSRAM
  .bss:             > MSMCSRAM
  .init_array:      > MSMCSRAM
  .far:             > MSMCSRAM
  .fardata:         > MSMCSRAM
  .neardata         > MSMCSRAM
  .rodata           > MSMCSRAM
  .data:            > MSMCSRAM
  .data:pte:pte_lvl1_0000000000000000 > EXTMEMPAGE
  .data:pte:pte_lvl0 > EXTMEMPAGE
  .data:pte:pte_lvl2_40000000 > EXTMEMPAGE
  .data:pte:pte_lvl2_80000000 > EXTMEMPAGE
  .data:pte:pte_lvl3_64800000 > EXTMEMPAGE
  .data:pte:pte_lvl3_64E00000 > EXTMEMPAGE
  .data:pte:pte_lvl3_64D00000 > EXTMEMPAGE
  .data:pte:pte_lvl3_64D20000 > EXTMEMPAGE
  .data:pte:pte_lvl3_64D40000 > EXTMEMPAGE
  .data:pte:pte_lvl3_64D60000 > EXTMEMPAGE
  .data:pte:pte_lvl3_64D80000 > EXTMEMPAGE
  .data:pte:pte_lvl3_64DA0000 > EXTMEMPAGE
  .data:pte:pte_lvl3_64DC0000 > EXTMEMPAGE
  .data:pte:pte_lvl3_64DE0000 > EXTMEMPAGE
  .data:pte:pte_lvl3_70000000 > EXTMEMPAGE
  .data:pte:pte_lvl3_70200000 > EXTMEMPAGE
  .data:pte:pte_lvl3_70400000 > EXTMEMPAGE
  .data:pte:pte_lvl3_70600000 > EXTMEMPAGE
  .data:pte:pte_lvl3_80000000 > EXTMEMPAGE
  .data:pte:pte_lvl3_80200000 > EXTMEMPAGE
  .data:pte:pte_lvl3_80400000 > EXTMEMPAGE
  .data:pte:pte_lvl3_80600000 > EXTMEMPAGE
  .data:pte:pte_lvl3_80800000 > EXTMEMPAGE
  .data:pte:pte_lvl3_80A00000 > EXTMEMPAGE
  .data:pte:pte_lvl3_80C00000 > EXTMEMPAGE
  .data:pte:pte_lvl3_80E00000 > EXTMEMPAGE
  .data:pte:pte_lvl3_81000000 > EXTMEMPAGE
  .data:pte:pte_lvl3_81200000 > EXTMEMPAGE
  .data:pte:pte_lvl3_81400000 > EXTMEMPAGE
  .data:pte:pte_lvl3_81600000 > EXTMEMPAGE
  .data:pte:pte_lvl3_81800000 > EXTMEMPAGE
  .data:pte:pte_lvl3_81A00000 > EXTMEMPAGE
  .data:pte:pte_lvl3_81C00000 > EXTMEMPAGE
  .data:pte:pte_lvl3_81E00000 > EXTMEMPAGE

  .switch:          > MSMCSRAM
  .stack:           > MSMCSRAM
  .args:            > MSMCSRAM align = 0x4, fill = 0 {_argsize = 0x200; }
  .sysmem:          > L2SRAM
  .cinit:           > MSMCSRAM
  .const:           > MSMCSRAM START(const_start) SIZE(const_size)
  .pinit:           > MSMCSRAM
  .cio:             > MSMCSRAM
  .stack:           > MSMCSRAM
  .ddrData          > EXTMEM_DATACN
  .staticData       > EXTMEM_STATIC
  .msmcData         > MSMCSRAM
   xdc.meta:        > MSMCSRAM, type = COPY
#endif

}
#endif

2. The build instructions for FFTLIB mention that the test cases can be run in No Boot mode. What modifications need to be done to run these test cases in Boot mode (with Linux booting from the SD card)? Also, .lib of FFTLIB assume what addresses of L1 and L2?

https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-j784s4/09_02_00_05/exports/docs/fftlib_09_02_00_04/docs/user_guide/build_instructions_linux.html

Thanks,

Madhu

+1 Asha Bhandarkar 5 months ago in reply to MadhuBala E

TI__Genius 10170 points

Hi Madhu,

It looks like your colleagues have already posted the same questions on this thread:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1414326/processor-sdk-j784s4-understanding-l2-cache-and-more

I have already provided a response there regarding this issue. I suggest we contain the conversation there to keep this conversation streamlined and avoid confusion with duplicate questions.

I'll be closing this thread and your other duplicate thread for clarity. Let's continue to discuss at the link above as necessary.

Best,

Asha

0 MadhuBala E 5 months ago in reply to Asha Bhandarkar

Intellectual 255 points

Hi Asha

Thanks for the response

Madhu

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PROCESSOR-SDK-J784S4: PROCESSOR-SDK-J784S4: Understanding memory section in FFTlib