AM6411: Processors forum

Hello YOSHINORI KODAMA

Are you considering using the Ethernet Boot?

Please refer below errata

i2331 CPSW: Device lockup when reading CPSW registers

i2329 MDIO: MDIO interface corruption (CPSW and PRU-ICSS)

Regards.

Sreenivasa

Hello Sreenivasa

Thank you for your reply

"Ethernet boot should not be used on this device."

This thing is understood.Thank you for the information.

However, I would like to use CLKOUT0 to reduce the number of crystal devices used for RGMII PHY.

Therefore, I would like to know the jitter performance of CLKOUT0.

Regards.

Kodama

Hello YOSHINORI KODAMA

Thank you. 

YOSHINORI KODAMA said:

I decide to connect another device's CLK to the RGMII PHY.

Ok.

Are you able to share the use case for me to check and provide any additional input that i could get from the experts.

This is going to take some time but i can check.

Regards,

Sreenivasa

Hello Sreenivasa

Thank you.

correction.
CLK tolerance is 50ppm.
not jitter.

AM6411 connection with RGMII PHY for Ethernet communicates. RGMII PHY requires CLK25MHz.
I want to output CLK25MHz from AM6411.
I would like to know if the CLK is within 50ppm when output from CLKOUT0 of AM6411.
In addition, connect a 25MHz 0.5ppm TCXO to the input CLK pin MCU_OSC0_XI of AM6411.

Regards.

Kodama

Hello YOSHINORI KODAMA

Thank you. 

The CLKOUT0 PPM accuracy has dependency on the MCU_OSC0_XI  clock specification.

With the spec you mentioned, i do not see any concern meeting the RGMII clock PPM requirements.

(+) [FAQ] AM6442: CLKOUT0 feedback to RMII_REF_CLK always necessary? - Processors forum - Processors - TI E2E support forums

Be sure to follow the guidelines in the data sheet when external oscillator is used.

Regards,

Sreenivasa

Hello Sreenivasa

Thank you for confirming.

I would like to know how far the accuracy of CLK input to MCU_OSC0_XI can be reduced.

Is it 5ppm, 10ppm or 30ppm?

Please let me know.

Regards.

Kodama

Hello YOSHINORI KODAMA

Thank you. 

Please refer below:

The 50PPM error must be combination of the initial frequency error and the frequency error introduced by temperature variation and aging of the clock source across the system's entire operating range.

You must include all of the contributors when selecting a crystal. In most cases you will find it is necessary to select a 20PPM or 30PPM crystal so the remaining 30PPM or 20PPM allows enough margin for temperature variation and aging.

Regards,

Sreenivasa