Tool/software:
Is PCLK direction wrong in the block diagram? it should be output.
There should be a clock source from PLL in the block diagram like in Figure 12-452.
From TRM, there are two clock for DSS, but there is not a DSS block diagram have the two clock, even in the clock tree tool.
12.9.1.4.1.2 DISPC Clocks
DISPC has one clock domain for its internal logic and separate domains for each video port output.
The DISPC functional clock (DSS_FUNC_CLK) serves as the internal logic clock and also acts as the interface
clock for the DISPC initiator and responder ports to system interconnect. There is no internal divisor on this
clock.
The DISPC pixel clocks (DPI_x_IN_CLK) serve as the clocks for the DISPC video port outputs to OLDITX0
and OLDITX1 modules (VP1 pixel clock DPI_0_IN_CLK) or for the parallel display interface (VP2 pixel clock
DPI_1_IN_CLK). There are no internal divisors on the pixel clocks.
The frequency of DSS_FUNC_CLK clock must be greater or equal to the DPI_x_IN_CLK clocks, in order
to get the DISPC internal logic to function properly. The frequency of the DPI_x_IN_CLK clocks depend on
the output display resolution and required frame rate. For the maximum supported frequency ratings, refer to
device-specific Datasheet.
